LTC4352
7
4352fa
operaTion
The LTC4352 controls either single or back-to-back
N-channel MOSFETs in order to emulate an ideal diode.
Dual MOSFETs eliminate current flow from the input to the
output in an input undervoltage or overvoltage condition.
When enabled, an amplifier (AMP) monitors the voltage
between the V
IN
and OUT pins, and drives the GATE pin.
The amplifier controls the gate of the external MOSFET
to servo its forward voltage drop (V
IN
– OUT) to 25mV.
The gate voltage rises to enhance the MOSFET if the load
current causes more than 25mV of drop. For large output
currents the MOSFET gate is driven fully on and the voltage
drop is equal to I
LOAD
• R
DS(ON)
.
In the case of an input supply short-circuit, when the
MOSFET is conducting, a large reverse current starts
flowing from the load towards the input. The AMP detects
this failure condition as soon as it appears, and turns off
the MOSFET by pulling down the GATE pin. The REV pin
can be used to allow reverse current, overriding the diode
behavior.
The AMP quickly pulls-up the GATE pin whenever it senses
a large forward voltage drop. An external capacitor between
the CPO and SOURCE pins is needed for fast gate pull-up.
This capacitor is charged up, at device power-up, by the
internal charge-pump. This stored charge is used for the
fast gate pull-up.
The GATE pin sources current from the CPO pin, and sinks
current to the SOURCE and GND pins. Internal clamps
limit the GATE to SOURCE voltage to 6.1V, and the CPO to
SOURCE voltage to 6.7V.
The same clamps also limit the CPO
and GATE pins to a diode voltage below the SOURCE pin.
OV, UV, and V
CC
comparators, CP1 to CP3, control power
passage. The MOSFET is held off whenever the OV pin
is above 0.5V, the UV pin is below 0.5V, or the V
CC
pin is
below 2.57V. There is a 40µs delay from all three condi-
tions becoming good to GATE being allowed to turn on.
Overvoltage causes a fast turn-off, while undervoltage
activates a 100μA pull-down on GATE after a 7μs delay.
Open-drain pull-down, M1, pulls the STATUS pin low when
the GATE to SOURCE voltage exceeds 0.7V, to indicate that
power is passing through the MOSFET. The FAULT output,
M2, pulls low during an undervoltage or overvoltage fault
condition. It also pulls low when GATE is fully on and
the forward voltage drop exceeds 250mV, indicating the
MOSFET has too much current or has failed open circuit.
Note that this open MOSFET fault does not turn off the
MOSFET unlike the undervoltage and overvoltage faults.
LDO is a low dropout regulator that generates a 4.1V
supply at the V
CC
pin from the V
IN
input. When a supply
below 2.9V is being ORed, an external supply in the 2.9V
to 6V range is required at the V
CC
pin. Comparator CP4
will disable LDO when V
IN
is below V
CC
.
LTC4352
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High availability systems often employ parallel-connected
power supplies or battery feeds to achieve redundancy
and enhance system reliability. ORing diodes have been
a popular means of connecting these supplies at the
point of load. Diodes with storage capacitors also hold
up supply voltages when an input voltage sags or has a
brownout. The disadvantage of these approaches is the
diode’s significant forward voltage drop and the resulting
power loss. Additionally, diodes provide no information
concerning the status of the sourcing supply. Separate
control must therefore be added to ensure that a supply
that is out of range is not allowed to affect the load.
The LTC4352 solves these problems by using an external
N-channel MOSFET as the pass element (see Figure 1).
The MOSFET is turned on when power is being passed,
allowing for a low voltage drop from the supply to the load.
When the input source voltage drops below the output
common supply voltage it turns off the MOSFET, thereby
matching the function and performance of an ideal diode.
Power Supply Configuration
The LTC4352 can operate with supplies down to 0V. This
requires powering the V
CC
pin with an always present
external supply in the 2.9V to 6V range. If not always
present, a series 470Ω resistor or Schottky diode limits
device power dissipation and backfeeding of low V
CC
supply when V
IN
is high. For a 2.9V to 4.7V V
CC
supply,
V
IN
should be lower than V
CC
. A 0.1µF bypass capacitor
should also be connected between the V
CC
and GND pins,
close to the device. Figure 2 illustrates this.
If V
IN
operates above 2.9V then the external supply at
V
CC
is not needed. The 0.1µF capacitor is still required
for bypassing.
applicaTions inForMaTion
Figure 1. 12V Ideal Diode with Status and Fault Indicators
V
CC
UV
OV
REV
LTC4352
STATUS
FAULT
0.1µF
C2
R4
2.7k
D1
D1: GREEN LED LN1351C
D2: RED LED LN1261CAL
MOSFET
ON
FAULT
D2
R5
2.7k
C1
TO LOAD
12V
Q1
Si7336ADP
0.1µF
4352 F01
CPO V
IN
SOURCE GATE
GND
OUT
Figure 2. Power Supply Configurations
V
CC
LTC4352
TO LOAD
0V TO V
CC
V
IN
GATE OUT
0.1µF
2.9V TO 4.7V
GND
V
CC
LTC4352
TO LOAD
0V TO 18V
4352 F02
V
IN
GATE OUT
GND
V
CC
LTC4352
TO LOAD
2.9V TO 18V
V
IN
GATE OUT
0.1µF
GND
0.1µF
4.7V TO 6V
LTC4352
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Figure 3. Start-up Waveform for Single MOSFET Application
VOLTAGE
(5V/DIV)
TIME (2.5ms/DIV)
4352 FO3
CPO
GATE
OUT
V
IN
, SOURCE
V
CC
V
IN
= 5V
C2 = 0.1µF
applicaTions inForMaTion
N-channel MOSFETs. The maximum allowable drain-source
voltage, BV
DSS
, must be higher than the supply voltages
as the full supply voltage can appear across the MOSFET
when the input falls to 0V.
The FAULT pin pulls low to signal an open MOSFET fault
whenever the forward voltage drop across the enhanced
MOSFET exceeds 250mV. The R
DS(ON)
should be small
enough to conduct the maximum load current while not
triggering such a fault (when using FAULT), and to stay
within the MOSFETs power rating at the maximum load
current.
CPO Capacitor Selection
The recommended value of the capacitor between the
CPO and SOURCE pins is approximately 10x the input
capacitance, C
ISS
, of the MOSFET. A larger capacitor takes
a correspondingly longer time to charge up by the internal
charge pump. A smaller capacitor suffers more voltage
drop during a fast gate turn-on event as it shares charge
with the MOSFET gate capacitance.
CPO and GATE Start-Up
In single MOSFET applications, CPO is initially pulled up
to a diode below the SOURCE pin (Figure 3). In back-to-
back MOSFET applications, CPO starts off at 0V, since
SOURCE is near ground (Figure 4). CPO starts ramping
up 10µs after V
CC
clears its undervoltage lockout level.
Another 40µs later, GATE will also start ramping up with
CPO if UV, OV and V
IN
– OUT conditions allow it to. The
ramp rate is decided by the CPO pull-up current into the
combined CPO and GATE pin capacitances. An internal
clamp limits the CPO voltage to 6.7V above SOURCE,
while the final GATE voltage is determined by the forward
drop servo amplifier.
MOSFET Selection
The LTC4352 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFET are
its threshold voltage, the maximum drain-source voltage
BV
DSS
, and the on-resistance R
DS(ON)
.
The gate drive for the MOSFET is guaranteed to be between
5V and 7.5V. This allows the use of logic level threshold
Figure 4. Start-up Waveform for Back-to-Back MOSFET Application
VOLTAGE
(5V/DIV)
TIME (2.5ms/DIV)
4352 FO4
CPO
GATE
OUT
V
IN
V
CC
V
IN
= 5V
C2 = 0.1µF

LTC4352CDD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Management Specialized - PMIC L V Ideal Diode Cntr w/ Mon ing
Lifecycle:
New from this manufacturer.
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