Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications
Datasheet
SMSC EMC1182 13 Revision 1.0 (07-11-13)
DATASHEET
Chapter 4 System Management Bus Interface Protocol
4.1 Communications Protocol
The EMC1182 communicates with a host controller, such as an SMSC SIO, through the SMBus. The
SMBus is a two-wire serial communication protocol between a computer host and its peripheral
devices. A detailed timing diagram is shown in
Figure 4.1.
For the first 15ms after power-up the device may not respond to SMBus communications.
.
4.1.1 SMBus Start Bit
The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic
‘0’ state while the SMBus Clock line is in a logic ‘1’ state.
4.1.2 SMBus Address and RD / WR Bit
The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If
this RD / WR bit is a logic ‘0’, the SMBus Host is writing data to the client device. If this RD / WR bit
is a logic ‘1’, the SMBus Host is reading data from the client device.
The EMC1182-A SMBus slave address is determined by the pull-up resistor on the THERM pin as
shown in
Table 4.1, "SMBus Address Decode".
The Address decode is performed by pulling known currents from VDD through the external resistor
causing the pin voltage to drop based on the respective current / resistor relationship. This pin voltage
is compared against a threshold that determines the value of the pull-up resistor.
Figure 4.1 SMBus Timing Diagram
Table 4.1 SMBus Address Decode
PULL UP RESISTOR ON
THERM
PIN (±5%) SMBUS ADDRESS
4.7k 1111_100(r/w
)b
6.8k 1011_100(r/w
)b
SMDATA
SMCLK
T
BUF
P
S
S - Start Condition
P - Stop Condition
PS
T
HIGH
T
LOW
T
HD:STA
T
SU:STO
T
HD:STA
T
HD:DAT
T
SU:DAT
T
SU:STA
T
FALL
T
RISE
Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications
Datasheet
Revision 1.0 (07-11-13) 14 SMSC EMC1182
DATASHEET
The EMC1182-1 SMBus address is hard coded to 1001_100(r/w).
The EMC1182-2 SMBus address is hard coded to 1001_101(r/w).
4.1.3 THERM Pin Considerations
Because of the decode method used to determine the SMBus Address, it is important that the pull-up
resistance on the
THERM pin be within the tolerances shown in Table 4.1. Additionally, the pull-up
resistor on the THERM pin must be connected to the same 3.3V supply that drives the VDD pin.
For 15ms after power up, the THERM pin must not be pulled low or the SMBus address will not be
decoded properly. If the system requirements do not permit these conditions, the THERM pin must be
isolated from its hard-wired OR’d bus during this time.
One method of isolating this pin is shown in Figure 4.4, "Isolating the THERM pin".
4.1.5 SMBus Data Bytes
All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.
4.1.6 SMBus ACK and NACK Bits
The SMBus client will acknowledge all data bytes that it receives. This is done by the client device
pulling the SMBus data line low after the 8th bit of each byte that is transmitted. This applies to the
Write Byte protocol.
The Host will NACK (not acknowledge) the last data byte to be received from the client by holding the
SMBus data line high after the 8th data bit has been sent.
10k 1001_100(r/w)b
15k 1101_100(r/w
)b
22k 0011_100(r/w
)b
33k 0111_100(r/w
)b
Figure 4.4 Isolating the THERM
pin
Table 4.1 SMBus Address Decode (continued)
PULL UP RESISTOR ON
THERM
PIN (±5%) SMBUS ADDRESS
+3.3V
Shared THERM
22K
4.7K -
33K
+2.5 - 5V
EMC1182
8
7
6
5
SMDATA
SMCLK
1
2
3
4
ALERT / ADDR
VDD
DP
DN
THERM
GND
Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications
Datasheet
SMSC EMC1182 15 Revision 1.0 (07-11-13)
DATASHEET
4.1.7 SMBus Stop Bit
The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic
‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the device detects an SMBus Stop bit
and it has been communicating with the SMBus protocol, it will reset its client interface and prepare
to receive further communications.
4.1.8 SMBus Timeout
The EMC1182 supports SMBus Timeout. If the clock line is held low for longer than t
TIMEOUT
, the
device will reset its SMBus protocol. This function can be enabled by setting the TIMEOUT bit (see
Section 6.11, "Consecutive ALERT Register 22h").
4.1.9 SMBus and I
2
C Compatibility
The EMC1182 is compatible with SMBus and I
2
C. The major differences between SMBus and I
2
C
devices are highlighted here. For more information, refer to the SMBus 2.0 and I
2
C specifications. For
information on using the EMC1182 in an I
2
C system, refer to SMSC AN 14.0 SMSC Dedicated Slave
Devices in I
2
C Systems.
1. EMC1182 supports I
2
C fast mode at 400kHz. This covers the SMBus max time of 100kHz.
2. Minimum frequency for SMBus communications is 10kHz.
3. The SMBus client protocol will reset if the clock is held at a logic ‘0’ for longer than 30ms. This
timeout functionality is disabled by default in the EMC1182 and can be enabled by writing to the
TIMEOUT bit. I
2
C does not have a timeout.
4. I
2
C devices do not support the Alert Response Address functionality (which is optional for SMBus).
Attempting to communicate with the EMC1182 SMBus interface with an invalid slave address or invalid
protocol will result in no response from the device and will not affect its register contents. Stretching
of the SMCLK signal is supported, provided other devices on the SMBus control the timing.
4.2 SMBus Protocols
The device supports Send Byte, Read Byte, Write Byte, Receive Byte, and the Alert Response Address
as valid protocols as shown below.
All of the below protocols use the convention in Table 4.1.
Table 4.1 Protocol Format
DATA SENT
TO DEVICE
DATA SENT TO
THE HOST
# of bits sent # of bits sent

EMC1182-1-AIA-TR

Mfr. #:
Manufacturer:
Microchip Technology
Description:
Board Mount Temperature Sensors 1.8V SMBus Dual Tmp Sensor /w Alerts
Lifecycle:
New from this manufacturer.
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