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PE45450A-X

P1-P3P4-P6P7-P9P10-P12
Document No. DOC-44314-5 │ www.psemi.com
Page 1 of 12
©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Voltage Control and ESD
RF1
V
CTRL
RF2
P
OUT
P1dB
P
IN
DOC-62357
Product Description
The PE45450 is a HaRP™ technology-enhanced power
limiter designed for use in high performance power
limiting applications in test and measurement equipment,
radar, military electronic counter measure receivers and
wireless infrastructure transceivers and antennas.
Unlike traditional PIN diode solutions, the PE45450
achieves an adjustable input 1 dB compression point or
limiting threshold via a low current control voltage (V
CTRL
),
eliminating the need for external bias components, such
as DC blocking capacitors, RF choke inductors, and bias
resistors.
It delivers low insertion loss and high linearity under non-
limiting input power levels and extremely fast response
and recovery time in a limiting event. It also offers
superior ESD rating and ESD protection for subsequent
circuitry.
The PE45450 is manufactured on Peregrine’s
UltraCMOS
®
process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate.
Peregrine’s HaRP™ technology enhancements deliver
high linearity and excellent harmonics performance. It is
an innovative feature of the UltraCMOS process, offering
the performance of GaAs with the economy and
integration of conventional CMOS.
Product Specification
UltraCMOS
®
Power Limiter
9 kHz–6 GHz
Figure 1. Functional Diagram
PE45450
Features
 Monolithic drop-in solution with no
external bias components reducing
design complexity
 Adjustable power limiting threshold
from +25 dBm to +35 dBm
 Max power handling
 +40 dBm CW (10W)
 +47 dBm Pulsed (50W)
 Superior ESD rating and ESD protection
 8 kV HBM on all pins
 1 kV CDM on all pins
 600V MM on all pins
 Unbiased power limiting operation
 Fast response and recovery time of 1 ns
 Dual mode operation
 Power limiting mode
 Power reflecting mode
Figure 2. Package Type
12-lead 3x3 mm QFN
Product Specification
PE45450
Page 2 of 12
©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-44314-5 │ UltraCMOS
®
RFIC Solutions
Table 1. Electrical Specifications @ +25°C (Z
S
= Z
L
= 50Ω), unless otherwise noted
Parameter Condition
Min
Typ
Max
Unit
Operating frequency 9 kHz 6 GHz As shown
Power limiting mode
Insertion loss
1
9 kHz–3 GHz
3–6 GHz
0.45
0.80
0.70
1.05
dB
dB
Return loss
1
9 kHz–3 GHz
3–6 GHz
13
17
dB
dB
P1dB / limiting threshold
V
CTRL
= –2.5V @ 915 MHz
V
CTRL
= –1.5V @ 915 MHz
V
CTRL
= –0.5V @ 915 MHz
35
32
25
dBm
dBm
dBm
Leakage power
2
V
CTRL
= –2.5V @ 915 MHz
V
CTRL
= –1.5V @ 915 MHz
V
CTRL
= –0.5V @ 915 MHz
33.5
33
31.5
35.5
35
33.5
dBm
dBm
dBm
Leakage power slope V
CTRL
= –1.0V @ 915 MHz 0.4 dB/dB
Unbiased leakage power
2
V
CTRL
= 0V @ 915 MHz 25 27 dBm
Input IP2
V
CTRL
= –2.5V @ 915 MHz
V
CTRL
= –2.5V @ 6 GHz
115
110
dBm
dBm
Input IP3
V
CTRL
= –2.5V @ 915 MHz
V
CTRL
= –2.5V @ 6 GHz
70
60
dBm
dBm
Response / recovery time 1 GHz 1 ns
Power reflecting mode
3
Leakage power
2
V
CTRL
= +2.5V @ 915 MHz 2 8 dBm
Switching time
4
State change to 10% RF 400 µs
Notes: 1. External matching is required to achieve the performance.
2. Measured with +40 dBm CW applied at input.
3. This mode requires the control voltage to toggle between +2.5V and –2.5V. At +2.5V, the limiter equivalent
circuit is a low impedance to ground, reflecting most of the incident power back to the source.
4. State change is V
CTRL
toggle from –2.5V to +2.5V.
Product Specification
PE45450
Page 3 of 12
Document No. DOC-44314-5 │ www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Table 2. Pin Descriptions
Figure 3. Pin Configuration (Top View)*
Pin No. Pin Name Description
1, 3, 4, 6,
7, 9
GND Ground
2 RF1* RF port 1
5 V
CTRL
Control voltage
8 RF2* RF port 2
Pad GND Exposed pad: Ground for proper operation
10–12 N/C No connect
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE45450 in the 12-lead 3x3 mm QFN package is
MSL1.
Table 3. Operating Ranges
Parameter
Symbol
Min Typ Max Unit
Control voltage
Power limiting mode
Power reflecting mode
V
CTRL
–2.5
–2.5
–0.5
+2.5
V
V
RF input power, CW
1
P
MAX,CW
40 dBm
RF input power, pulsed
2
P
MAX,PULSED
47 dBm
Operating temperature
range
T
OP
–55 +25 +85 °C
Operating junction
temperature
1
T
J
+290 °C
RF input power, unbiased
2,3
P
MAX,UNB
47 dBm
Table 4. Absolute Maximum Ratings
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Notes: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7)
2. Machine Model (JEDEC JESD22-A115)
3. Charged Device Model (JEDEC JESD22-C101)
Parameter
Symbol
Min Max Unit
Control voltage
Power limiting mode
Power reflecting mode
V
CTRL
–3.3 3.6 V
Storage temperature range T
ST
–65 +150 °C
ESD voltage HBM
1
, all pins V
ESD,HBM
8000 V
ESD voltage MM
2
, all pins V
ESD,MM
600 V
ESD voltage CDM
3
, all pins V
ESD,CDM
1000 V
Notes: 1. CW, 100% duty cycle, in 10 min, 50Ω
2. Pulsed, 0.1% duty cycle of 1 µs pulse width in 10 min, 50Ω
3. V
CTRL
= 0V or V
CTRL
pin left not connected
Note: * Pins 10–12 can be ground if deemed necessary by the customer.
Note: * RF pins 2 and 8 must be at 0 VDC. The RF pins do not require DC
blocking capacitors for proper operation if the 0 VDC requirement is met.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified.
P1-P3P4-P6P7-P9P10-P12

PE45450A-X

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RF POWER LIMITER 6GHZ 50W 12QFN
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