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PE45450A-X

P1-P3P4-P6P7-P9P10-P12
Product Specification
PE45450
Page 7 of 12
Document No. DOC-44314-5 │ www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 8. P
OUT
vs. P
IN
Over V
CTRL
Figure 9. P
OUT
vs. P
IN
Over Frequency @
V
CTRL
= –0.7V
Figure 11. P
OUT
vs. P
IN
Over Frequency @
V
CTRL
= –1.5V
Typical Performance Data @ +25°C, 915 MHz (Z
S
= Z
L
= 50Ω), unless otherwise noted
Figure 10. P1dB vs. V
CTRL
Over Temperature
0
5
10
15
20
25
30
35
40
10 15 20 25 30 35 40
Pout(dBm)
Pin(dBm)
–2.5V –1.5V –0.7V –0.5V 0V 2.5V
0
5
10
15
20
25
30
35
40
10 15 20 25 30 35 40
Pout(dBm)
Pin(dBm)
–0.7V@915MHz –0.7V@3GHz –0.7V@6GHz
0
5
10
15
20
25
30
35
40
10 15 20 25 30 35 40
Pout(dBm)
Pin(dBm)
–1.5V@915MHz –1.5V@3GHz –1.5V@6GHz
15
20
25
30
35
40
‐2.5 ‐2 ‐1.5 ‐1 ‐0.5
P1dB(dBm)
VCTRL (V)
P1dB@–55°C(dBm) P1dB@25°C(dBm) P1dB@85°C(dBm)
Product Specification
PE45450
Page 8 of 12
©2013-2014 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-44314-5 │ UltraCMOS
®
RFIC Solutions
Figure 13. IIP3 / IIP2 vs. P
IN
Over V
CTRL
Figure 15. P1dB, IIP3, IIP2, Leakage Power @
P
MAX
vs. V
CTRL
Figure 12. IIP3 / IIP2 vs. V
CTRL
Over Temperature
Typical Performance Data @ +25°C, 915 MHz (Z
S
= Z
L
= 50Ω), unless otherwise noted
30
40
50
60
70
80
90
100
110
120
130
‐2.5 ‐2 ‐1.5 ‐1 ‐0.5
IIP3/IIP2(dBm)
V
CTRL
(V)
IIP3@–55°C(dBm) IIP3@25°C(dBm) IIP3@85°C(dBm)
IIP2@–55°C(dBm) IIP2@25°C(dBm) IIP2@85°C(dBm)
20
30
40
50
60
70
80
90
100
110
120
130
140
10 15 20 25 30 35
IIP3/IIP2(dBm)
Pin(dBm)
IIP3@VCTRL=–2.5V(dBm) IIP2@VCTRL=–2.5V(dBm) IIP3@VCTRL=–1.5V(dBm)
IIP2@VCTRL=–1.5V(dBm) IIP3@VCTRL=–0.7V(dBm) IIP2@VCTRL=–0.7V(dBm)
IIP3@VCTRL=–0.5V(dBm) IIP2@VCTRL=–0.5V(dBm)
18
20
22
24
26
28
30
32
34
36
38
20
30
40
50
60
70
80
90
100
110
120
‐2.5 ‐2 ‐1.5 ‐1 ‐0.5
LeakagePower@P
max
(dBm)
IIP3/IIP2/P1dB(dBm)
V
CTRL
(V)
IIP3(dBm) IIP2(dBm) P1dB(dBm) LeakagePower@Pmax
Figure 14. Leakage Power @ P
MAX
vs. V
CTRL
Over Temperature
‐10
‐5
0
5
10
15
20
25
30
35
40
‐2.5 ‐2 ‐1.5 ‐1 ‐0.5 0 0.5 1 1.5 2 2.5
LeakagePower(dBm)
V
CTRL
(V)
LeakagePower(–55°C)@Pmax LeakagePower(25°C)@Pmax
LeakagePower(85°C)@Pmax
Product Specification
PE45450
Page 9 of 12
Document No. DOC-44314-5 │ www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Evaluation Kit
The power limiter EVK board was designed to
ease customer evaluation of Peregrine’s
PE45450. The bi-directional RF input and
output are connected to RF1 and RF2 port
through a 50Ω transmission line via SMA
connectors J2 and J3. A through 50Ω
transmission line is available via SMA
connectors J5 and J6. This transmission line
can be used to estimate the loss of the PCB
over the environmental conditions being
evaluated. The 2-pin connector J4 is
connected to the external bias V
CTRL
.
The board is constructed of a four metal layer
material with a total thickness of 62 mils. The
top RF layer is Rogers RO4350B material with
a 6.6 mil RF core and Er = 3.66. The middle
layers provide ground for the transmission
lines. The transmission lines were designed
using a coplanar waveguide with ground plane
model using a trace width of 13.5 mils, trace
gaps of 10 mils, and metal thickness of
2.1 mils.
Figure 16. Evaluation Board Layout
PRT-51452
P1-P3P4-P6P7-P9P10-P12

PE45450A-X

Mfr. #:
Buy PE45450A-X
Manufacturer:
Description:
RF POWER LIMITER 6GHZ 50W 12QFN
Lifecycle:
New from this manufacturer.
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