TLE4253
General Product Characteristics
Data Sheet 6 Rev. 1.2, 2009-11-09
4.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3 Thermal Resistance
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
4.2.1 Input Voltage
V
I
3.5 40 V V
I
≥ V
Q
+ V
dr
4.2.1 Adjust / Enable Input Voltage
(Voltage Tracking Range)
V
ADJ/EN
2.0 – V –
4.2.2 Junction Temperature
T
j
-40 150 °C–
4.2.3 Output Capacitor Requirements
C
Q
10 µF –
1)
1) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%.
4.2.4 ESR
CQ
–5 Ω –
2)
2) relevant ESR value at f = 10 kHz.
Pos. Parameter Symbol Limit Value Unit Conditions
Min. Typ. Max.
PG-DSO-8:
4.3.1 Junction to Soldering Point
R
thJSP
– 39 – K/W Pins 2 - 3 and 6 - 7
fixed to
T
A
4.3.2 Junction to Ambient R
thJA
– 150 – K/W Footprint only
1)
1) Package mounted on PCB FR4; 80 x 80 x 1.5 mm; 35 µm Cu, 5 µm Sn; horizontal position; zero airflow.
Not subject to production test; specified by design.
4.3.3 – 91 – K/W 300 mm
2
PCB heatsink
area
1)
4.3.4 – 81 – K/W 600 mm
2
PCB heatsink
area
1)
4.3.5 – 65 – K/W 2s2p board
2)
2) Specified R
thJA
value is according to JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip+package)
was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the package contacted the first inner copper layer.
PG-DSO-8 exposed pad:
4.3.6 Junction to Case Bottom
R
thJC
– 9 – K/W Measured to exposed
bottom pad
4.3.7 Junction to Ambient
R
thJA
– 169 – K/W Footprint only
1)
4.3.8 – 64 – K/W 300 mm
2
PCB heatsink
area
1)
4.3.9 – 55 – K/W 600 mm
2
PCB heatsink
area
1)
4.3.10 – 49 – K/W 2s2p board
2)
