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A1445EEWLT-P

P1-P3P4-P6P7-P9
Low-Voltage Full-Bridge Brushless DC Motor Driver
with Hall Commutation, Externally Controlled Speed Regulation, Soft Switching,
and Reverse Battery, Short Circuit, and Thermal Shutdown Protection
A1444 and
A1445
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Two typical application circuits are shown in figures 1 and 2.
The application circuit in figure 1 shows the device S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
pin
controlled by the user. In this case, the device is powered continu-
ously and the average supply current would switch between low
and high values depending on the state of the S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
pin.
Figure 2 illustrates an applications circuit where the device sup-
ply pin and S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
pin are connected together. When power is
applied to the device, it enters enable mode and operates with
high average supply current.
Note that:
• No external diode is required for reverse battery protection
because the protection is fully integrated into the IC.
• Thermal shutdown also is integrated to protect the device against
inadvertent output shorts during manufacturing or testing.
• In these figures, the PDC pin is tied to GND. Alternatively, the
PDC pin could be tied to any of the voltage rails or left floating,
which will determine the internal PWM duty cycle as specified
in the Electrical Characteristics table.
Application Information
M
+
V
BATT
C
BYP
A1444
A1445
PDC
VDD
I/O
System Logic
Control
GND
VOUT1
SLEEP VOUT2
Figure 1. Application circuit showing user-controlled sleep/enable mode, while the
A144x remains powered at all times
M
+
V
BATT
C
BYP
A1444
A1445
PDC
VDD
I/O
System Logic
Control
GND
VOUT1
SLEEP VOUT2
Figure 2. Application circuit showing simultaneous user control of power supply and
sleep mode.
Low-Voltage Full-Bridge Brushless DC Motor Driver
with Hall Commutation, Externally Controlled Speed Regulation, Soft Switching,
and Reverse Battery, Short Circuit, and Thermal Shutdown Protection
A1444 and
A1445
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Power Derating
The device must be operated below the maximum junction tem-
perature of the device, T
J
(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the appli-
cation. This section presents a procedure for correlating factors
affecting operating T
J
. (Thermal data is also available on the
Allegro MicroSystems website.)
The package thermal resistance, R
θJA
, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the effective thermal conductivity, K, of
the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, R
θJC
, is relatively
small component of R
θJA
. Ambient air temperature, T
A
, and air
motion are significant external factors, damped by overmolding.
The effect of varying power levels (Power Dissipation, P
D
), can
be estimated. The following formulas represent the fundamental
relationships used to estimate T
J
, at various P
D
levels.
P
D
= V
IN
× I
IN
(1)
ΔT = P
D
× R
θJA
(2)
T
J
= T
A
+ ΔT (3)
For a load of 30 Ω, and given common conditions such as:
T
A
= 25°C, V
DD
= 3 V, I
DD
= 85 mA, V
LOAD
= 2.43 V,
I
LOAD
= 83 mA, and R
θJA
= 250 °C/W,
then:
P
D
= V
DD
× I
DD
– V
LOAD
× I
LOAD
= 3 V × 83 mA – 2.43 V × 81 mA
= 52.17 mW
ΔT = P
D
× R
θJA
= 52.17 mW × 250 °C/W
= 13°C
T
J
= T
A
+ ΔT
= 25°C + 13°C
= 38°C
A worst-case estimate, P
D
(max), represents the maximum allow-
able power level, without exceeding T
J
(max), at a selected R
θJA
and T
A
.
Low-Voltage Full-Bridge Brushless DC Motor Driver
with Hall Commutation, Externally Controlled Speed Regulation, Soft Switching,
and Reverse Battery, Short Circuit, and Thermal Shutdown Protection
A1444 and
A1445
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright ©2009, Allegro MicroSystems, Inc.
The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283; 5,389,889;
5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Package EW, 6 pin MLP/DFN
SEATING
PLANE
0.38 ±0.02
0.70 ±0.10 1.25 ±0.05
0.25 ±0.05
1.10 ±0.10
1.10
0.30
0.70 1.575
0.50
0.325
2.00 ±0.15
1.50 ±0.15
C0.08
7X
0.325
+0.055
–0.045
0.50 BSC
A
1
1
6
6
1
6
A
Terminal #1 mark area
B
Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
For Reference Only, not for tooling use (refernce DWG-2856; similar to
JEDEC Type 1, MO-229X2BCD)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
C
Reference land pattern layout (reference IPC7351
SON50P200X200X100-9M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
Active Area Depth 0.15 mm REF
E
E
C
B
Hall Element (not to scale)
F
F
F
F
0.94
0.99
PCB Layout Reference View
C
Branding scale and appearance at supplier discretion
G
G
D
D
Coplanarity includes exposed thermal pad and terminals
Standard Branding Reference View
N = Last two digits of device part number
Y = Last digit of year of manufacture
W = Week of manufacture
NN
YWW
1
P1-P3P4-P6P7-P9

A1445EEWLT-P

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Manufacturer:
Description:
IC MOTOR DRIVER 1.8V-4.2V 6DFN
Lifecycle:
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