LTC3729
8
3729fb
RUN/SS (Pin 1/Pin 28): Combination of Soft‑Start, Run
Control Input and Short‑Circuit Detection Timer. A capaci‑
tor to ground at this pin sets the ramp time to full current
output. Forcing this pin below 0.8V causes the IC to shut
down all internal circuitry. All functions are disabled in
shutdown.
SENSE1
+
, SENSE2
+
(Pins 2,14/Pins 30, 12): The (+)
Input to the Differential Current Comparators. The I
TH
pin voltage and built‑in offsets between SENSE
–
and
SENSE
+
pins in conjunction with R
SENSE
set the current
trip threshold.
SENSE1
–
, SENSE2
–
(Pins 3, 13/Pins 31, 11): The (–)
Input to the Differential Current Comparators.
EAIN (Pin 4/Pin 1): Input to the Error Amplifier that com‑
pares the feedback voltage to the internal 0.8V reference
voltage. This pin is normally connected to a resistive divider
from the output of the differential amplifier (DIFFOUT).
PLLFLTR (Pin 5/Pin 2):
The Phase‑Locked Loop’s Low
Pass Filter is tied to this pin. Alternatively, this pin can
be driven with an AC or DC voltage source to vary the
frequency of the internal oscillator.
PLLIN (Pin 6/Pin 3): External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
with 50kΩ. The phase‑locked loop will force the rising
top gate signal of controller 1 to be synchronized with
the rising edge of the PLLIN signal.
PHASMD (Pin 7/Pin 4): Control Input to Phase Selector
which determines the phase relationships between control‑
ler 1, controller 2 and the CLKOUT signal.
I
TH
(Pin 8/Pin 5): Error Amplifier Output and Switching
Regulator Compensation Point. Both current comparator’s
thresholds increase with this control voltage. The normal
voltage range of this pin is from 0V to 2.4V.
SGND (Pin 9/Pin 6): Signal Ground, common to both con‑
trollers, must be routed separately from the input switched
current ground path to the common (–) terminal(s) of the
C
OUT
capacitor(s).
V
DIFFOUT
(Pin 10/Pin 7): Output of a Differential Amplifier
that provides true remote output voltage sensing. This pin
normally drives an external resistive divider that sets the
output voltage.
V
OS
–
, V
OS
+
(Pins 11, 12/Pins 8, 9): Inputs to an Operational
Amplifier. Internal precision resistors capable of being
electronically switched in or out can configure it as a dif‑
ferential amplifier or an uncommitted Op Amp.
PGOOD (Pin 15/Pin 13):
Open‑Drain Logic Output. PGOOD
is pulled to ground when the voltage on the EAIN pin is
not within ±7.5% of its set point.
TG2, TG1 (Pins 16, 27/Pins 14, 26): High Current Gate
Drives for Top N‑Channel MOSFETS. These are the outputs
of floating drivers with a voltage swing equal to INTV
CC
superimposed on the switch node voltage SW.
SW2, SW1 (Pins 17, 26/Pins 15, 25): Switch Node
Connections to Inductors. Voltage swing at these pins
is from a Schottky diode (external) voltage drop below
ground to V
IN
.
BOOST2, BOOST1 (Pins 18, 25/Pins 17, 24): Bootstrapped
Supplies to the Topside Floating Drivers. Capacitors
are connected between the Boost and Switch pins and
Schottky diodes are tied between the Boost and INTV
CC
pins. Voltage swing at the Boost pins is from INTV
CC
to
(V
IN
+ INTV
CC
).
BG2, BG1 (Pins 19, 23/Pins 18, 22): High Current Gate
Drives for Bottom Synchronous N‑Channel MOSFETS.
Voltage swing at these pins is from ground to INTV
CC
.
PGND (Pin 20/Pin 19): Driver Power Ground. Connect
to sources of bottom N‑channel MOSFETS and the (–)
terminals of C
IN
.
INTV
CC
(Pin 21/Pin 20): Output of the Internal 5V Linear
Low Dropout Regulator and the EXTV
CC
Switch. The driver
and control circuits are powered from this voltage source.
Decouple to power ground with a 1µF ceramic capacitor
placed directly adjacent to the IC and minimum of 4.7µF
additional tantalum or other low ESR capacitor.
PIN FUNCTIONS
G Package/UH Package
