SA572
http://onsemi.com
7
Basic Expandor
Figure 6 shows an application of the circuit as a simple
expandor. The gain expression of the system is given by:
V
OUT
V
IN
+
ǒ
2
I
1
@
R
3
@ V
IN(AVG)
R
2
@ R
1
Ǔ
2
(eq. 4)
(I
1
= 140 A)
Both the resistors R
1
and R
2
are tied to internal summing
nodes. R
1
is a 6.8 k internal resistor. The maximum input
current into the gain cell can be as large as 140 A. This
corresponds to a voltage level of 140 A•6.8 k = 952 mV
peak. The input peak current into the rectifier is limited to
300 A by the internal bias system. Note that the value of
R
1
can be increased to accommodate higher input level. R
2
and R
3
are external resistors. It is easy to adjust the ratio of
R
3
/R
2
for desirable system voltage and current levels. A
small R
2
results in higher gain control current and smaller
static and dynamic tracking error. However, an impedance
buffer A
1
may be necessary if the input is voltage driven
with large source impedance.
The gain cell output current feeds the summing node of
the external OPA A
2
. R
3
and A
2
convert the gain cell output
current to the output voltage. In high-performance
applications, A
2
has to be low-noise, high-speed and wide
band so that the high-performance output of the gain cell
will not be degraded. The non-inverting input of A
2
can be
biased at the low noise internal reference Pin 6 or 10.
Resistor R
4
is used to bias up the output DC level of A
2
for
maximum swing. The output DC level of A
2
is given by:
V
OUT
DC + V
REF
ǒ
1 )
R
3
R
4
Ǔ
* V
B
R
3
R
4
(eq. 5)
V
B
can be tied to a regulated power supply for a dual
supply system and be grounded for a single supply system.
C
A
sets the attack time constant and C
R
sets the recovery
time constant.
−
+
A1
(7,9)
(3,13)
(8)
(16)
(4,12)
(2,14)
(6,10)
(5,11)
BUFFER
A2
V
OUT
V
IN
C
IN1
C
IN2
C
IN3
V
REF
+VB
+V
CC
G
10F1F
2.2F
2.2F
2.2F
Figure 6. Basic Expandor Schematic
R
5
100k
R
2
3.3k
6.8k
17.3k
1k
R
4
R
3
R
1
R
6
C
1
C
R
C
A
2.2F
Basic Compressor
Figure 7 shows the hook-up of the circuit as a
compressor. The IC is put in the feedback loop of the OPA
A
1
. The system gain expression is as follows:
V
OUT
V
IN
+
ǒ
I
1
2
@
R
2
@ R
1
R
3
@ V
IN(AVG)
Ǔ
1
2
(eq. 6)
(I
1
= 140 A)
R
DC1
, R
DC2
, and CDC form a DC feedback for A
1
. The
output DC level of A
1
is given by:
V
OUT
DC + V
REF
ǒ
1 )
R
DC1
) R
DC2
R
4
Ǔ
* V
B
@
ǒ
R
DC1
) R
DC2
R
4
Ǔ
(eq. 7)
The zener diodes D
1
and D
2
are used for channel
overload protection.
