AD7912/AD7922
Rev. 0 | Page 22 of 32
DAISY-CHAIN EXAMPLE
In applications where fast throughput is not critical, connecting
several ADCs in a daisy chain lets the user perform simultane-
ous sampling on all the ADCs contained in the chain using the
minimum number of I/O lines from the µC/DSP ports.
The user needs to alternate modes of operation in the ADCs.
While the parts are in normal mode, the conversion is per-
formed and the result from each ADC is stored in its internal
register. Following the conversion, the parts are placed into
daisy-chain mode and the user can proceed to read the result
from each ADC by shifting the data from one ADC to the next.
For clarity in the following example, only two devices are
connected in a daisy chain. Both AD7912/AD7922 are
addressed by the same
CS
and SCLK signal. The devices are
configured as shown in Figure 33 for simultaneous conversion
and shifting read operation later. The output of the device on
the left, ADC1, feeds the input of the device on the right, ADC2.
During a normal conversion, the conversion result is stored
internally and output to the DOUT pin. In daisy-chain mode,
the value internally stored is output through the DOUT pin and
the information provided at the DIN pin is shifted into the
internal register.
When several AD7912/AD7922 are connected in a daisy chain,
the sequence is as follows:
1.
Normal conversion.
Every AD7912/AD7922 performs a conversion on its
selected channel and the result is stored in the internal shift
register.
2.
Entering daisy-chain mode.
In this cycle,
CS
is brought high between the 10th and
12th SCLK falling edges and all the devices enter daisy-
chain mode.
3.
Daisy-chain cycles.
While the AD7912/AD7922 are in daisy-chain mode, the
conversion results from all the devices in the chain are
read, and the parts are configured for the next conversion.
The user needs to perform as many read cycles as there are
devices in the chain. To keep all the AD7912/AD7922 in
daisy-chain mode, the CHN and STY bits in the DIN input
must always be inverted. Data is shifted through the
devices in the chain. Data is clocked into the device in the
chain by the same clock used to clock data out. The first
word clocked into the DIN pin once the devices are in
daisy-chain mode is eventually lost. The second word
clocked into the DIN pin contains the channel configura-
tion data for the last device in the chain, the third word
clocked into the DIN pin contains the channel configura-
tion data for the second last device in the chain, and so on.
Then the selected channel for the first device in the chain is
clocked in the cycle executed after all the data has been
read, that is, in the short cycle used to change modes of
operation. See Figure 34.
4.
Enter normal mode.
After reading the conversion results from the AD7912/
AD7922, the devices need to be placed into normal mode
to perform a new conversion. Therefore, in this cycle
CS
is
brought high between the 10th and the 13th SCLK falling
edge. The DOUT line contains invalid data and DIN
contains the selected channel for the first device in the
chain. The remaining devices in the chain have already set
the channel for the next conversion as a result of the data
shifted in during daisy-chain mode.
5.
Normal conversion.
A new conversion can be performed on the newly selected
channels. The process can be repeated by following the
previous steps.
Figure 34 shows the timing diagram for two AD7912/
AD7922 connected in a daisy chain, as shown in Figure 33.
The DIN signal corresponds to the DIN pin on the first
AD7912/AD7922 in the chain, and the DOUT signal
corresponds to the DOUT pin on the last AD7912/AD7922
in the chain. The words clocked into the DIN pin, which
set up the channel for the next conversion for the two
AD7912/AD7922, are shown as COMMAND1 and
COMMAND2. The first word clocked in, COMMAND3,
does not remain in any of the ADCs in the chain and is
eventually lost. The channel configuration data for the first
device in the chain, COMMAND1, is clocked in while
changing from daisy-chain mode to normal mode.
Figure 35 is a more detailed diagram that shows the data
presented on the DIN pin and clocked out on the DOUT
pin for each of the AD7912/AD7922 in Figure 33. If the
DOUT1 (or DIN2) signal is ignored, Figure 35 brings
about Figure 34.
04351-0-030
SCLK
DIN1 DOUT1
ADC1
CS
SCLK
CS
SCLK
DIN2 DOUT2
ADC2
CS
DIN DOUT
FSX
SCLK
TX
DR
µC/DSP
Figure 33. AD7912/AD7922 Connected in Daisy Chain
AD7912/AD7922
Rev. 0 | Page 23 of 32
04351-0-031
SCLK
CS
DOUT
DON'T CARE DON'T CARE VALID DATA ADC2 VALID DATA ADC1 DON'T CAREDON'T CARE
NORMAL MODE
CONVERSION ON THE
TWO DEVICES
NORMAL MODE
CONVERSION ON THE
TWO DEVICES
CHANGE MODE
CS HIGH
BETWEEN THE
10TH–12TH SCLK
FALLING EDGE
DAISY-CHAIN MODE
DATA IS SHIFTED
FROM ONE ADC TO
THE NEXT ONE
DAISY-CHAIN MODE
DATA IS SHIFTED
FROM ONE ADC TO
THE NEXT ONE
DIN
DON'T CARE DON'T CARE CH
STY CH
STY DON'T CAREDON'T CARE
THE DATA WILL BE
EVENTUALLY LOST,
COMMAND3
SET CHANNEL
FOR ADC2,
COMMAND2
SET CHANNEL
FOR ADC1,
COMMAND1
CHANGE MODE
CS HIGH BETWEEN THE
10TH–13TH SCLK
FALLING EDGE
KEEP THE DEVICES IN
DAISY-CHAIN MODE
Figure 34. Daisy-Chain Diagrams—1
04351-0-032
NORMAL CONVERSION DAISY-CHAIN CYCLE
THE PARTS ENTER
DAISY-CHAIN MODE
1 16 1 10 1 10 12 14 16
SCLK
CS
DIN
DOUT
DOUT1
(DIN2)*
12
DON'T CARE DON'T CARE COMMAND3 WITH CHN
STY
0, 0, CHN = MOD, VALID DATA ADC1
(0, 0, CHN = STY, VALID DATA ADC1)
DON'T CARE
0, 0, CHN
MOD, VALID DATA ADC1
(0, 0, CHN
STY, VALID DATA ADC1)
0, 0, CHN = MOD, VALID DATA ADC2 DON'T CARE
0, 0, CHN
MOD, VALID DATA ADC2
NOTE
*INFORMATION IN BRACKETS CORRESPONDS TO DATA CLOCKED INTO DIN2 PIN
SCLK
CS
DIN
DOUT
DOUT1
(DIN2)*
COMMAND2 WITH CHN
STY COMMAND1 DON'T CARE
COMMAND3 COMMAND2
0, 0, CHN = MOD, VALID DATA ADC1
(0, 0, CHN = STY, VALID DATA ADC1)
0, 0, CHN
MOD, VALID DATA ADC1 COMMAND3
0, 0, CHN = MOD, VALID DATA ADC2
DAISY-CHAIN CYCLE NORMAL CONVERSION
THE PARTS ENTER
NORMAL MODE
1 10121416 1 10 13 1 16
SHIFTED INTO THE ADC1 INTERNAL REGISTER,
THIS DATA WILL BE EVENTUALLY LOST
SHIFTED INTO THE ADC2
INTERNAL REGISTER
SHIFTED INTO THE ADC1
INTERNAL REGISTER
SHIFTED INTO THE ADC1 INTERNAL REGISTER, IT
CONTAINS CHANNEL FOR NEXT CONVERSION ON ADC1
SHIFTED INTO THE ADC2
INTERNAL REGISTER
SHIFTED INTO THE ADC2 INTERNAL REGISTER, IT
CONTAINS CHANNEL FOR NEXT CONVERSION ON ADC2
Figure 35. Daisy-Chain Diagrams—II
AD7912/AD7922
Rev. 0 | Page 24 of 32
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7912/AD7922 when
not converting, the average power consumption of the ADC
decreases at lower throughput rates. Figure 36 shows how, as the
throughput rate is reduced, the device remains in its power-
down state longer and the average power consumption over
time drops.
For example, if the AD7912/AD7922 are operating in a continu-
ous sampling mode with a throughput rate of 100 kSPS and a
SCLK of 18 MHz (V
DD
= 5 V), and the devices are placed in the
power-down mode between conversions, then the power
consumption is calculated as follows. The power dissipation
during normal operation is 20 mW (V
DD
= 5 V). If the power-up
time is one dummy cycle (1 µs), and the remaining conversion
time is another cycle (1 µs), then the AD7912/AD7922 dissipate
20 mW for 2 µs during each conversion cycle. If the throughput
rate is 100 kSPS and the cycle time is 10 µs, then the average
power dissipated during each cycle is
(2/10) × (20 mW) = 4 mW
If V
DD
= 3 V, SCLK = 18 MHz, and the device is again in power-
down mode between conversions, then the power dissipation
during normal operation is 6 mW. The AD7912/AD7922 now
dissipate 6 mW for 2 µs during each conversion cycle. With a
throughput rate of 100 kSPS, the average power dissipated
during each cycle is
(2/10) × (6 mW) = 1.2 mW
In the previous calculations, the power dissipation when the
part is in power-down mode has not been taken into account.
By placing the parts into power-down mode between conver-
sions, the average power consumed by the ADC decreases as
the throughput rate decreases, because the ADC remains in a
power-down state for a longer time.
Figure 36 shows the power consumption versus throughput rate
when using the power-down mode between conversions with
both 5 V and 3 V supplies.
Power-down mode is intended for use with throughput rates of
approximately 330 kSPS and under, because at higher sampling
rates the short time spent in power-down does not affect the
average power consumed by the ADC.
100
0.01
0.1
1
10
0 50 100 150 200 250 300 350
04351-0-033
THROUGHPUT (kSPS)
POWER (mW)
V
DD
= 5V, SCLK = 18MHz
V
DD
= 3V, SCLK = 18MHz
Figure 36. Power Consumption vs. Throughput Rate

AD7912AUJZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 2CH 2.35-5.25V 1 MSPS 10-Bit
Lifecycle:
New from this manufacturer.
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