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AD7912AUJZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
AD7912/AD7922
Rev. 0 | Page 25 of 32
SERIAL INTERFACE
Figure 37 and Figure 38 show the detailed timing diagrams for
serial interfacing to the AD7922 and AD7912, respectively. The
serial clock provides the conversion clock and also controls the
transfer of information from the AD7912/AD7922 during
conversion.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
puts the track-and-hold into hold mode,
takes the bus out of three-state. The analog input is sampled at
this point and the conversion is initiated.
For the AD7922, the conversion requires 16 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next SCLK rising edge, as
shown in Figure 37 at Point B. On the 16th SCLK falling edge,
the DOUT line goes back into three-state. If the rising edge of
CS
occurs before 16 SCLKs have elapsed, then the conversion is
terminated and the DOUT line goes back into three-state.
Otherwise, DOUT returns to three-state on the 16th SCLK
falling edge, as shown in Figure 37. Sixteen serial clock cycles
are required to perform the conversion process and to access
data from the AD7922.
For the AD7912, the conversion requires 14 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next SCLK rising edge, as
shown in Figure 38 at Point B.
If the rising edge of
CS
occurs before 14 SCLKs have elapsed,
then the conversion is terminated and the DOUT line goes back
into three-state. If 16 SCLKs are considered in the cycle, DOUT
returns to three-state on the 16th SCLK falling edge, as shown
in Figure 38.
CS
going low clocks out the first leading zero to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges beginning with the
second leading zero. Therefore, the first falling clock edge on
the serial clock has the first leading zero provided and also
clocks out the second leading zero. The final bit in the data
transfer is valid on the 16th falling edge, having been clocked
out on the previous (15th) falling edge.
In applications with a slower SCLK, it is possible to read in data
on each SCLK rising edge. In that case, the first falling edge of
SCLK clocks out the second leading zero and it can be read in
the first rising edge. However, the first leading zero that is
clocked out when
CS
goes low is missed, unless it is read on the
first falling SCLK edge. The 15th falling edge of SCLK clocks
out the last bit and it can be read in the 15th rising SCLK edge.
If
CS
goes low just after the SCLK falling edge has elapsed,
CS
clocks out the first leading zero as before and it can be read in
the SCLK rising edge. The next SCLK falling edge clocks out
the second leading zero and it can be read in the following
rising edge.
04351-0-034
ZERO
X
12345 13141516
X CHN STY X X X XX
CHN MOD DB11 DB10 DB2 DB1 DB0Z
t
2
t
6
t
4
t
8
t
9
t
3
t
7
t
5
t
10
t
1
t
QUIET
t
CONVERT
SCLK
CS
DOUT
THREE-STATE THREE-STATE
DIN
B
Figure 37. AD7922 Serial Interface Timing Diagram
04351-0-035
ZERO
X
12345 13141516
X CHN STY X X X XX
CHN MOD DB9 DB8 DB0 ZERO ZEROZ
t
2
t
6
t
4
t
8
t
9
t
3
t
7
t
5
t
10
t
1
t
QUIET
t
CONVERT
SCLK
CS
DOUT
THREE-STATE
THREE-STATE
TWO TRAILING ZEROS
DIN
B
Figure 38. AD7912 Serial Interface Timing Diagram
AD7912/AD7922
Rev. 0 | Page 26 of 32
MICROPROCESSOR INTERFACING
The serial interface on the AD7912/AD7922 allows the parts to
be directly connected to a range of microprocessors. This
section explains how to interface the AD7912/AD7922 with
some of the more common microcontroller and DSP serial
interface protocols.
AD7912/AD7922 to TMS320C541 Interface
The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7912/AD7922. The
CS
input allows easy interfacing between
the TMS320C541 and the AD7912/AD7922 without any glue
logic required. The serial port of the TMS320C541 is set up to
operate in burst mode (FSM = 1 in the serial port control
register, SPC) with the internal serial clock CLKX (MCM = 1 in
the SPC register) and the internal frame signal (TXM = 1 in the
SPC register); therefore, both pins are configured as outputs. For
the AD7922, the word length should be set to 16 bits (FO = 0 in
the SPC register). This DSP allows frames with a word length of
16 bits or 8 bits only. In the AD7912, therefore, where 14 bits are
required, the FO bit should be set up to 16 bits, and 16 SCLKs
are needed. For the AD7912, two trailing zeros are clocked out
in the last two clock cycles.
The values in the SPC register are as follows:
FO = 0
FSM = 1
MCM = 1
TXM = 1
To implement the power-down mode on the AD7912/AD7922,
the format bit, FO, can be set to 1, which sets the word length to
8 bits.
The connection diagram is shown in Figure 39. Note that, for
signal processing applications, the frame synchronization signal
from the TMS320C541 must provide equidistant sampling.
AD7912/
AD7922*
TMS320C541*
CLKX
DR
FSX
FSR
SCLK
DOUT
CS
CLKR
DX
DIN
04351-0-036
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 39. Interfacing to the TMS320C541
AD7912/AD7922 to ADSP-218x
The ADSP-218x family of DSPs are interfaced directly to the
AD7912/AD7922 without any glue logic required. The SPORT
control register should be set up as follows:
TFSW = RFSW = 1, alternate framing
INVRFS = INVTFS = 1, active low frame signal
DTYPE = 00, right-justify data
ISCLK = 1, internal serial clock
TFSR = RFSR = 1, frame every word
IRFS = 0, set up RFS as an input
ITFS = 1, set up TFS as an output
SLEN = 1111, 16 bits for the AD7922
SLEN = 1101, 14 bits for the AD7912
To implement the power-down mode, SLEN should be set to
0111 to issue an 8-bit SCLK burst. The connection diagram is
shown in Figure 40. The ADSP-218x has the TFS and RFS of the
SPORT tied together, with TFS set as an output and RFS set as
an input. The DSP operates in alternate framing mode and the
SPORT control register is set up as described previously. The
frame synchronization signal generated on the TFS is tied to
CS
and, as with all signal processing applications, equidistant
sampling is necessary. However, in this example, the timer
interrupt is used to control the sampling rate of the ADC and,
under certain conditions, equidistant sampling might not be
achieved.
AD7912/
AD7922*
ADSP-218x*
SCLK
RFS
TFS
SCLK
CS
DR
DOUT
DT
DIN
04351-0-037
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 40. Interfacing to the ADSP-218x
The timer registers are loaded with a value that provides an
interrupt at the required sample interval. When an interrupt is
received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and, therefore, the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given, that is, TX0 = AX0, the state of the SCLK is checked.
The DSP waits until the SCLK has gone high, low, and high
again before transmission starts. If the timer and SCLK values
are chosen such that the instruction to transmit occurs on or
near the rising edge of SCLK, the data might be transmitted or
it might wait until the next clock edge.
AD7912/AD7922
Rev. 0 | Page 27 of 32
For example, the ADSP-2189 has a master clock frequency of
40 MHz. If the SCLKDIV register is loaded with the value of 3,
then an SCLK of 5 MHz is obtained, and eight master clock
periods elapse for every one SCLK period. Depending on the
throughput rate selected, if the timer register is loaded with the
value 803 (803 + 1 = 804), then 100.5 SCLK occur between
interrupts and subsequently between transmit instructions. This
situation results in nonequidistant sampling, because the
transmit instruction occurs on a SCLK edge. If the number of
SCLKs between interrupts is a whole integer figure of N, then
equidistant sampling is implemented by the DSP.
AD7912/AD7922 to DSP563xx Interface
The connection diagram in Figure 41 shows how the AD7912/
AD7922 can be connected to the SSI (synchronous serial
interface) of the DSP563xx family of DSPs from Motorola. The
SSI is operated in synchronous and normal mode (SYN = 1 and
MOD = 0 in the Control Register B, CRB) with internally
generated word frame sync for both Tx and Rx (Bits FSL1 = 0
and FSL0 = 0 in the CRB). Set the word length in the Control
Register A (CRA) to 16 by setting bits WL2 = 0, WL1 = 1, and
WL0 = 0 for the AD7922. This DSP does not offer the option for
a 14-bit word length, so the AD7912 word length is set up to
16 bits like the AD7922. For the AD7912, the conversion process
uses 16 SCLK cycles, with the last two clock periods clocking
out two trailing zeros to fill the 16-bit word.
To implement the power-down mode on the AD7912/AD7922,
the word length can be changed to 8 bits by setting Bits
WL2 = 0, WL1 = 0, and WL0 = 0 in CRA. The FSP bit in the
CRB register can be set to 1, which means that the frame goes
low and a conversion starts. Likewise, by means of the Bits
SCD2, SCKD, and SHFD in the CRB register, the Pin SC2 (the
frame sync signal) and SCK in the serial port are configured as
outputs, and the MSB is shifted first.
The values are as follows:
MOD = 0
SYN = 1
WL2, WL1, WL0 depend on the word length
FSL1 = 0, FSL0 = 0
FSP = 1, negative frame sync
SCD2 = 1
SCKD = 1
SHFD = 0
Note that, for signal processing applications, the frame
synchronization signal from the DSP563xx must provide
equidistant sampling.
AD7912/
AD7922*
DSP563xx*
SCK
SCLK
SRD
DOUT
STD
DIN
SC2
CS
04351-0-038
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 41. Interfacing to the DSP563xx
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AD7912AUJZ-REEL7

Mfr. #:
Buy AD7912AUJZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 2CH 2.35-5.25V 1 MSPS 10-Bit
Lifecycle:
New from this manufacturer.
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