CY62158EV30LL-45ZSXIT

CY62158EV30 MoBL
®
Document Number: 38-05578 Rev. *J Page 4 of 18
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied .......................................... –55 °C to +125 °C
Supply Voltage to
Ground Potential ..........................–0.3 V to V
CC(max)
+ 0.3 V
DC Voltage Applied to Outputs
in High Z State
[3, 4]
.................... –0.3 V to V
CC(max)
+ 0.3 V
DC Input Voltage
[3, 4]
................. –0.3 V to V
CC(max)
+ 0.3 V
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) .................................> 2001 V
Latch up Current ....................................................> 200 mA
Operating Range
Product Range
Ambient
Temperature
(T
A
)
V
CC
[5]
CY62158EV30LL Industrial –40 °C to +85 °C 2.2 V–3.6 V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
45 ns
Unit
Min Typ
[6]
Max
V
OH
Output HIGH voltage I
OH
= –0.1 mA 2.0 V
I
OH
= –1.0 mA, V
CC
> 2.70 V 2.4 V
V
OL
Output LOW voltage I
OL
= 0.1 mA 0.4 V
I
OL
= 2.1 mA, V
CC
> 2.70 V 0.4 V
V
IH
Input HIGH voltage V
CC
= 2.2 V to 2.7 V 1.8 V
CC
+ 0.3 V V
V
CC
= 2.7 V to 3.6 V 2.2 V
CC
+ 0.3 V V
V
IIL
Input LOW voltage V
CC
= 2.2 V to 2.7 V –0.3 0.6 V
V
CC
= 2.7 V to 3.6 V –0.3 0.8 V
I
IX
Input leakage current GND < V
I
< V
CC
–1 +1 A
I
OZ
Output leakage current GND < V
O
< V
CC
, Output Disabled –1 +1 A
I
CC
V
CC
operating supply current f = f
max
= 1/t
RC
V
CC
= V
CCmax
I
OUT
= 0 mA
CMOS levels
–1825mA
f = 1 MHz 1.8 3 mA
I
SB1
Automatic CE power down
current — CMOS Inputs
CE
1
> V
CC
– 0.2 V, CE
2
< 0.2 V,
V
IN
> V
CC
– 0.2 V, V
IN
< 0.2 V,
f = f
max
(Address and Data Only),
f = 0 (
OE and WE), V
CC
= 3.60 V
–28A
I
SB2
[7]
Automatic CE Power down
Current — CMOS inputs
CE
1
> V
CC
– 0.2 V or CE
2
< 0.2 V,
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V,
f = 0, V
CC
= 3.60 V
–28A
Notes
3. V
IL(min)
= –2.0 V for pulse durations less than 20 ns.
4. V
IH(max)
= V
CC
+ 0.75 V for pulse duration less than 20 ns.
5. Full device AC operation assumes a 100 s ramp time from 0 to V
CC
(min) and 200 s wait time after V
CC
stabilization.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
7. Chip enables (
CE
1
and CE
2
) must be at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
CY62158EV30 MoBL
®
Document Number: 38-05578 Rev. *J Page 5 of 18
Capacitance
Parameter
[8]
Description Test Conditions Max Unit
C
IN
Input capacitance T
A
= 25 °C, f = 1 MHz, V
CC
= V
CC(typ)
10 pF
C
OUT
Output capacitance 10 pF
Thermal Resistance
Parameter
[8]
Description Test Conditions 48-ball BGA 44-pin TSOP II Unit
JA
Thermal resistance
(junction to ambient)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
72 76.88 C/W
JC
Thermal resistance
(junction to case)
8.86 13.52 C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
TH
Equivalent to:
THÉ VENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Fall time: 1 V/ns
Rise Time: 1 V/ns
Parameters 2.5 V 3.0 V Unit
R1 16667 1103
R2 15385 1554
R
TH
8000 645
V
TH
1.20 1.75 V
Note
8. Tested initially and after any design or process changes that may affect these parameters.
CY62158EV30 MoBL
®
Document Number: 38-05578 Rev. *J Page 6 of 18
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
[9]
Max Unit
V
DR
V
CC
for data retention 1.5 V
I
CCDR
[10]
Data retention current V
CC
= 1.5 V, CE
1
> V
CC
 0.2 V
or CE
2
< 0.2 V, V
IN
> V
CC
0.2 V
or V
IN
< 0.2 V
–25A
t
CDR
[11]
Chip deselect to data retention time 0 ns
t
R
[12]
Operation recovery time 45 ns
Data Retention Waveform
Figure 4. Data Retention Waveform
V
CC
, min
V
CC
, min
t
CDR
V
DR
>
1.5 V
t
R
CE
1
V
CC
CE
2
DATA RETENTI/ON MODE
or
Notes
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
10. Chip enables (
CE
1
and CE
2
) must be at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full Device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 s or stable at V
CC(min)
> 100 s.

CY62158EV30LL-45ZSXIT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM 8Mb 3V 45ns 1024K x 8 LP SRAM
Lifecycle:
New from this manufacturer.
Delivery:
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