10
Product Overview
Description
The ACPL-796J isolated sigma-delta () modulator
converts an analog input signal into a high-speed (up
to 20 MHz) single-bit data stream by means of a sigma-
delta over-sampling modulator. The time average of the
modulator data is directly proportional to the input signal
voltage. The modulator uses external clock ranges from 5
MHz to 20 MHz that is coupled across the isolation barrier.
This arrangement allows synchronous operation of data
acquisition to any digital controller, and adjustable clock
for speed requirements of the application. The modulator
data are encoded and transmitted across the isolation
boundary where they are recovered and decoded into
high-speed data stream of digital ones and zeros. The
original signal information is represented by the density
of ones in the data output.
The other main function of the modulator (optocoupler)
is to provide galvanic isolation between the analog signal
input and the digital data output. It provides high noise
margins and excellent immunity against isolation-mode
transients that allows direct measurement of low-level
signals in highly noisy environments, for example mea-
surement of moor phase currents in power inverters.
With 0.5 mm minimum DTI, the ACPL-796J provides reliable
double protection and high working insulation voltage,
which is suitable for fail-safe designs. This outstanding
isolation performance is superior to alternatives including
devices based on capacitive- or magnetic-coupling with
DTI in micro-meter range. O ered in an SO-16 package,
the isolated ADC delivers the reliability, small size, superior
isolation and over-temperature performance motor drive
designers need to accurately measure current at much
lower price compared to traditional current transducers.
Analog Input
The di erential analog inputs of the ACPL-796J are im-
plemented with a fully-di erential, switched-capacitor
circuit. The ACPL-796J accepts signal of ±200 mV (full scale
±320 mV), which is ideal for direct connection to shunt
based current sensing or other low-level signal sources
applications such as motor phase current measurement.
An internal voltage reference determines the full-scale
analog input range of the modulator (±320 mV); an input
range of ±200 mV is recommended to achieve optimal
performance. Users are able to use higher input range,
for example ±250 mV, as long as within full-scale range,
for purpose of over-current or overload detection. Figure
13 shows the simpli ed equivalent circuit of the analog
input.
Figure 13. Analog input equivalent circuit.
In the typical application circuit (Figure 17), the ACPL-796J
is connected in a single-ended input mode. Given the
fully di erential input structure, a di erential input con-
nection method (balanced input mode as shown in Figure
14) is recommended to achieve better performance. The
input currents created by the switching actions on both of
the pins are balanced on the  lter resistors and cancelled
out each other. Any noise induced on one pin will be
coupled to the other pin by the capacitor C and creates
only common mode noise which is rejected by the device.
Typical value for Ra and Rb is 22 and 10 nF for C.
Figure 14. Simpli ed di erential input connection diagram.
200Ω (TYP)
3 pF (TYP)
3 pF (TYP)
f
SWITCH
= MCLKIN
V
IN
+
V
IN
200Ω (TYP)
1.5 pF
1.5 pF
COMMON MODE
VOLTAGE
f
SWITCH
= MCLKIN
ANALOG
GROUND
V
IN
+
V
IN
ACPL-796J
V
DD1
GND1
5 V
+Analog Input
Ra
Rb
C
–Analog Input
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Latch-up Consideration
Latch-up risk of CMOS devices needs careful consider-
ation, especially in applications with direct connection to
signal source that is subject to frequent transient noise.
The analog input structure of the ACPL-796J is designed
to be resilient to transients and surges, which are often
encountered in highly noisy application environments
such as motor drive and other power inverter systems.
Other situations could cause transient voltages to the
inputs include short circuit and overload conditions. The
ACPL-796J is tested with DC voltage of up to –2 V and 2-
second transient voltage of up to –6 V to the analog inputs
and there is no latch-up or damage to the device.
Figure 15. Moudlator output vs. analog input.
Modulator Data Output
Input signal information is contained in the modulator
output data stream, represented by the density of ones
and zeros. The density of ones is proportional to the input
signal voltage, as shown in Figure 15. A di erential input
signal of 0 V ideally produces a data stream of ones 50%
of the time and zeros 50% of the time. A di erential input
of –200 mV corresponds to 18.75% density of ones, and
a di erential input of +200 mV is represented by 81.25%
density of ones in the data stream. A di erential input of
+320 mV or higher results in ideally all ones in the data
stream, while input of –320 mV or lower will result in all
zeros ideally. Table 10 shows this relationship.
–FS (ANALOG INPUT)
+FS (ANALOG INPUT)
0 V (ANALOG INPUT)
TIME
MODULATOR OUTPUT
ANALOG INPUT
Table 10. Input voltage with ideal corresponding density of 1s at modulator data output, and ADC code.
Analog Input Voltage Input Density of 1s ADC Code (16-bit unsigned decimation)
Full-Scale Range 640 mV
+Full-Scale +320 mV 100% 65,535
+Recommended Input Range +200 mV 81.25% 53,248
Zero 0 mV 50% 32,768
–Recommended Input Range –200 mV 18.75% 12,288
–Full-Scale –320 mV 0% 0
Notes:
1. With bipolar o set binary coding scheme, the digital code begins with digital 0 at –FS input and increases proportionally to the analog input until
the full-scale code is reached at the +FS input. The zero crossing occurs at the mid-scale input.
2. Ideal density of 1s at modulator data output can be calculated with V
IN
/640 mV + 50%; similarly, the ADC code can be calculated with (V
IN
/640 mV)
× 65,536 + 32,768, assuming a 16-bit unsigned decimation  lter.
12
Digital Filter
A digital  lter converts the single-bit data stream from
the modulator into a multi-bit output word similar to
the digital output of a conventional A/D converter. With
this conversion, the data rate of the word output is also
reduced (decimation). A Sinc
3
lter is recommended to
work together with the ACPL-796J. With a 10 MHz external
Note: In applications, a 0.1 F bypass capacitor must be connected between pins V
DD1
and
GND1, and between pins V
DD2
and GND2 of the ACPL-796J.
Figure 16. Typical application circuit with a Sinc
3
lter.
clock frequency, 256 decimation ratio and 16-bit word
settings, the output data rate is 39 kHz (= 10 MHz/256).
This  lter can be implemented in an ASIC, an FPGA or a
DSP. Some of the ADC codes with corresponding input
voltages are shown in Table 10.
ACPL-796J
3-WIRE
SERIAL
INTERFACE
INPUT
CURRENT
R
SHUNT
V
IN
+
V
IN
V
DD1
GND1
ISOLATED
5 V
0.1
PF
MCLKIN
MDAT
V
DD2
GND2
NON-
ISOLATED
5 V/3.3 V
0.1
PF
SINC
3
FILTER
CLOCK
DATA
GND
V
DD
SCLK
SDAT
CS
ISOLATION
BARRIER
GND1 GND2
10
PF
10
PF

ACPL-796J-000E

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
Optically Isolated Amplifiers 5MHz-20MHz,5000 Vrms Sigma-Delta Modulatr
Lifecycle:
New from this manufacturer.
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