Automotive PSoC
®
4: PSoC 4000
Family Datasheet
Programmable System-on-Chip (PSoC
®
)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-92145 Rev. *E Revised February 17, 2016
Programmable System-on-Chip (PSoC
®
)
General Description
PSoC
®
4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM
®
Cortex™-M0 CPU, while being AEC-Q100 compliant. It combines programmable and reconfigurable analog and digital blocks
with flexible automatic routing. The PSoC 4000 product family is the smallest member of the PSoC 4 platform architecture. It is a
combination of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense)
with best-in-class performance, and general-purpose analog. PSoC 4000 products will be fully upward compatible with members of
the PSoC 4 platform for new applications and design needs.
Features
32-bit MCU Subsystem
■ 16-MHz ARM Cortex-M0 CPU
■ Up to 16 KB of flash with Read Accelerator
■ Up to 2 KB of SRAM
Programmable Analog
■ Two current DACs (IDACs) for general-purpose or capacitive
sensing applications
■ One low-power comparator with internal reference
Low Power 1.71-V to 5.5-V operation
■ Deep Sleep mode with wake-up on interrupt and I
2
C address
detect
Capacitive Sensing
■ Cypress Capacitive Sigma-Delta (CSD) provides best-in-class
signal-to-noise ratio (SNR) and water tolerance
■ Cypress-supplied software component makes capacitive
sensing design easy
■ Automatic hardware tuning (SmartSense™)
Serial Communication
■ Multi-master I
2
C block with the ability to do address matching
during Deep Sleep and generate a wake-up on match
Timing and Pulse-Width Modulation
■ One 16-bit Timer/Counter/Pulse-Width Modulator (TCPWM)
block
■ Center-aligned, Edge, and Pseudo-Random modes
■ Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Up to 20 Programmable GPIO Pins
■ 24-pin QFN and 16-pin SOIC packages
■ GPIO pins on Ports 0, 1, and 2 can be CapSense or have other
functions
■ Drive modes, strengths, and slew rates are programmable
Temperature Ranges
■ A Grade: –40 °C to +85 °C
■ S-Grade: –40°C to +105 °C
■ Automotive Electronics Council (AEC) Q100 qualified
PSoC Creator Design Environment
■ Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
■ Applications Programming Interface (API) component for all
fixed-function and programmable peripherals
Industry-Standard Tool Compatibility
■ After schematic entry, development can be done with
ARM-based industry-standard development tools
