AT45DB011
7
Input Test Waveforms and
Measurement Levels
t
R
, t
F
< 5 ns (10% to 90%)
Output Test Load
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
I
SB
Standby Current CS, RESET, WP = V
IH
, all inputs at
CMOS levels
210µA
I
CC1
Active Current, Read Operation f = 13 MHz; I
OUT
= 0 mA; V
CC
= 3.6V 4 10 mA
I
CC2
Active Current, Program/Erase
Operation
V
CC
= 3.6V 10 25 mA
I
LI
Input Load Current V
IN
= CMOS levels 1 µA
I
LO
Output Leakage Current V
I/O
= CMOS levels 1 µA
V
IL
Input Low Voltage 0.6 V
V
IH
Input High Voltage 2.0 V
V
OL
Output Low Voltage I
OL
= 1.6 mA; V
CC
= 2.7V 0.4 V
V
OH
Output High Voltage I
OH
= -100 µA V
CC
- 0.2V V
AC Characteristics
Symbol Parameter Min Typ Max Units
f
SCK
SCK Frequency 13 MHz
t
WH
SCK High Time 35 ns
t
WL
SCK Low Time 35 ns
t
CS
Minimum CS High Time 250 ns
t
CSS
CS Setup Time 250 ns
t
CSH
CS Hold Time 250 ns
t
CSB
CS High to RDY/BUSY Low 200 ns
t
SU
Data In Setup Time 10 ns
t
H
Data In Hold Time 20 ns
t
HO
Output Hold Time 0 ns
t
DIS
Output Disable Time 25 ns
t
V
Output Valid 30 ns
t
XFR
Page to Buffer Transfer/Compare Time 120 200 µs
t
EP
Page Erase and Programming Time 10 20 ms
t
P
Page Programming Time 715ms
t
PE
Page Erase Time 610ms
t
BE
Block Erase Time 715ms
t
RST
RESET Pulse Width 10 µs
t
REC
RESET Recovery Time s
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
0.45V
2.0
0.8
2.4V
DEVICE
UNDER
TEST
30 pF
AT45DB011
8
AC Waveforms
Two different timing diagrams are shown below. Waveform
1 shows the SCK signal being low when CS
makes a high-
to-low transition, and Waveform 2 shows the SCK signal
being high when CS
makes a high-to-low transition. Both
waveforms show valid timing diagrams. The setup and hold
times for the SI signal are referenced to the low-to-high
transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI
Mode 0, and Waveform 2 shows timing that is compatible
with SPI Mode 3.
Waveform 1 Inactive Clock Polarity Low
Waveform 2 Inactive Clock Polarity High
CS
SCK
SI
SO
tCSS
VALID IN
tHtSU
tWH tWL tCSH
tCS
tV
HIGH IMPEDANCE
VALID OUT
tHO tDIS
HIGH IMPEDANCE
CS
SCK
SI
SO
tCSS
VALID IN
tHtSU
tWL tWH tCSH
tCS
tV
HIGH Z
VALID OUT
tHO tDIS
HIGH IMPEDANCE
AT45DB011
9
Reset Timing (Inactive Clock Polarity Low Shown)
Command Sequence for Read/Write Operations (Except Status Register Read)
Notes: 1. r designates bits reserved for larger densities.
2. It is recommended that r be a logical 0.
3. For densities larger than 1M bit, the r bits become the most significant Page Address bit for the appropriate density.
CS
SCK
RESET
SO
HIGH IMPEDANCE HIGH IMPEDANCE
SI
tRST
tREC tCSS
SI CMD 8 bits
8 bits
8 bits
MSB
Reserved for
larger densities
Page Address
(PA8-PA0)
Byte/Buffer Address
(BA8-BA0/BFA8-BFA0)
LSBr r r r r r X X X X X X X X X X X X X X X X X X

AT45DB011-JI

Mfr. #:
Manufacturer:
Description:
IC FLASH 1M SPI 15MHZ 32PLCC
Lifecycle:
New from this manufacturer.
Delivery:
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