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MK2049-36SILFTR

P1-P3P4-P6P7-P8
DATASHEET
3.3 VOLT COMMUNICATIONS CLOCK PLL MK2049-36
IDT®
3.3 VOLT COMMUNICATIONS CLOCK PLL 1
MK2049-36 REV G 051310
Description
The MK2049-36 is a Phased Locked Loop (PLL) based
clock synthesizer that accepts multiple input frequencies.
With an 8 kHz clock input as a reference, the MK2049-36
generates T1, E1, T3, E3, OC3 and other communications
frequencies. This allows for the generation of clocks
frequency-locked to an 8 kHz backplane clock, simplifying
clock synchronization in communications systems.
This part also has a jitter-attenuated Buffer capability. In this
mode, the MK2049-36 is ideal for filtering jitter from clocks
with high jitter.
IDT can customize these devices for many other different
frequencies. Contact your IDT representative for more
details.
Features
• Packaged in 20 pin SOIC
• Pb (lead) free package
• 3.3 V + 5% operation
• Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4, and 4E
• Accepts multiple inputs: 8 kHz backplane clock or 10 to
50 MHz
• Locks to 8 kHz + 100 ppm (External mode)
• Buffer Mode allows jitter attenuation of 10 - 50 MHz input
and x1/x0.5 or x1/x2 outputs
• Exact internal ratios enable zero ppm error
• Output clock rates include T1, E1, T3, E3, and OC3
submultiples
• See also the MK2049-34 and MK2049-45
Block Diagram
VCXO-BASED
PLL
(M
ASTER CLOCK
GENERATOR)
EXTERNAL PULLABLE CRYSTAL
FREQUENCY
MULTIPLYING
PLL
2
INPUT REFERENCE
CLOCK
(TYPICALLY 8KHZ)
C
LOCK OUTPUT
CLOCK OUTPUT / 2
8
KHZ (REGENERATED)
4
F
REQUENCY SELECT
MK2049-36
3.3 VOLT COMMUNICATIONS CLOCK PLL VCXO AND SYNTHESIZER
IDT®
3.3 VOLT COMMUNICATIONS CLOCK PLL 2
MK2049-36 REV G 051310
Pin Assignment
20 pin (300) mil SOIC
Pin Descriptions
16
1
15
2
14
FS1 FS0
3
13
X2
4
12
X1
RES
5
11
VDD
6
CAP2
7
FCAP
8
VDD
GND
CAP1
VDD
GND
GND
CLK
ICLK
9
10
CLK/2
FS3
8k
FS2
20
19
18
17
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 FS1 Input Frequency select 1. Determines CLK input/outputs per table on page 3.
Internal pull-up resistor.
2 X2 XO Crystal connection. Connect to a MHz crystal as shown in table on page 3.
3 X1 XI Crystal connection. Connect to a MHz crystal as shown in table on page 3.
4 VDD Power Power supply. Connect to +3.3 V.
5 FCAP - Filter capacitor. Connect a 1000 pF ceramic capacitor to ground.
6 VDD Power Power supply. Connect to +3.3 V.
7 GND Power Connect to ground
8 CLK Output Clock output determined by status of FS3:0 per tables on page 3.
9 CLK/2 Output Clock output determined by status of FS3:0 per tables page 3. Always 1/2 of
CLK.
10 8k Output Recovered 8 kHz clock output.
11 FS2 Input Frequency select 2. Determines CLK input/outputs per tables on page 3.
Internal pull-up resistor.
12 FS3 Input Frequency select 3. Determines CLK input/outputs per tables on page 3.
Internal pull-up resistor.
13 ICLK Input Input clock connection. Connect to 8 kHz backplane or MHz clock.
14 GND Power Connect to ground.
15 VDD Power Power Supply. Connect to +3.3 V.
16 CAP1 Loop
Filter
Connect the loop filter ceramic capacitors and resistor between this pin and
CAP2.
17 GND Power Connect to ground.
18 CAP2 Loop Connect the loop filter ceramic capacitors and resistor between this pin and
MK2049-36
3.3 VOLT COMMUNICATIONS CLOCK PLL VCXO AND SYNTHESIZER
IDT®
3.3 VOLT COMMUNICATIONS CLOCK PLL 3
MK2049-36 REV G 051310
Output Decoding Table - External Mode (MHz)
Output Decoding Table - Buffer Mode (MHz)
0 = connect directly to ground, 1 = connect directly to VDD or leave open.
Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
Operating Modes
The MK2049-36 has two operating modes: External and Buffer. Although both modes use an input clock to generate various
output clocks, there are important differences in their input and crystal requirements.
External Mode
The MK2049-36 accepts an external 8 kHz clock and will produce a number of common communication clock frequencies.
The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as narrow as 10 ns is acceptable.
Buffer Mode
Unlike the other two modes that accept only a single specified input frequency, Buffer Mode will accept a wider range of
input clocks. The input jitter is attenuated and the outputs on CLK and CLK/2 also provide the option of getting x1, x2, x4, or
1/2 of the input frequency. For example, this mode can be used to remove the jitter from a 27 MHz clock, generating
low-jitter 27 MHz and 13.5 MHz outputs.
19 RES - Connect a 10-200kΩ resistor to ground. Contact IDTfor recommended value
for your application.
20 FS0 Input Frequency select 0. Determines CLK input/outputs per table on page 3.
Internal pull-up resistor.
ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8k
Crystal
Used (MHz) N
8 kHz00001.5443.0888 kHz12.352 1544
8 kHz00012.0484.0968 kHz12.288 1536
8 kHz001022.36844.7368 kHz11.184 1398
8 kHz001117.18434.3688 kHz11.456 1432
8 kHz010077.76155.528 kHz 19.44 2430
8 kHz010116.38432.7688 kHz16.384 2048
8 kHz011014.35228.7048 kHz14.352 1794
8 kHz0111TESTTESTTEST TEST TEST
8 kHz100018.52837.0568 kHz18.528 2316
8 kHz100112.35224.7048 kHz24.704 3088
8 kHz1010 7.68 15.368 kHz 15.36 1920
8 kHz1011TESTTESTTEST TEST 1344
8 kHz110012.28824.5768 kHz24.576 3072
8 kHz110116.38432.7688 kHz12.288 1536
Pin
Number
Pin
Name
Pin
Type
Pin Description
ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8k Crystal N
22 - 361110ICLK/2ICLKN/AICLK/23
11 - 1811112*ICLK4*ICLKN/AICLK 3
P1-P3P4-P6P7-P8

MK2049-36SILFTR

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Description:
Clock Synthesizer / Jitter Cleaner 3.3 VOLT COMMUNICA. CLOCK VCXO PLL
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