MK2049-36
3.3 VOLT COMMUNICATIONS CLOCK PLL VCXO AND SYNTHESIZER
IDT®
3.3 VOLT COMMUNICATIONS CLOCK PLL 4
MK2049-36 REV G 051310
Frequency Locking to the Input
In all modes, the output clocks are frequency-locked to the input. The outputs will remain at the specified output frequency
as long as the combined variation of the input frequency and the crystal does not exceed 100 ppm. For example, if the
crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the input frequency can vary by up to 60 ppm and
still have the output clock remain frequency-locked.
PC Board Layout
A proper board layout is critical to the successful use of the MK2049. In particular, the CAP1 and CAP2 pins are very
sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as possible and the two
capacitors and resistor must be mounted next to the device as shown below. The capacitor shown between pins 15 and 17,
and the one between pins 4 and 7 are the power supply decoupling capacitors. The high frequency output clocks on pins 8
and 9 should have a series termination of 33Ω connected close to the pin. Additional improvements will come from keeping
all components on the same side of the board, minimizing vias through other signal layers, and routing other signals away
from the MK2049. You may also refer to application note MAN05 for additional suggestions on layout of the crystal selection.
The crystal traces should include pads for small capacitors from X1 and X2 to ground. These are used to adjust the stray
capacitance of the board to match the crystal load capacitance. The typical telecom reference frequency is accurate to
much less than 1 ppm, so the MK2049 may lock and run properly even if the board capacitance is not adjusted with these
fixed capacitors. However, IDT recommends that the adjustment capacitors be included to minimize the effects of variation
in individual crystals, temperature, and aging. The value of these capacitors (typically 0 - 4 pF) is determined once for a
given board layout, using the procedure found in application note MAN05 on the IDT web site.
External Component Selection
The MK2049-36 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01μF
must be connected between VDD and GND pins close to the chip (especially pins 4 and 7, 15 and 17), and 33Ω series
terminating resistors should be used on clock outputs with traces longer than one inch (assuming 50Ω traces). The selection
of additional external components is described in the following sections.
16
1
15
2
14
3
13
4
12
5
11
6
7
8
9
10
20
19
18
17
G
G
cap
cap
resist
cap
cap
cap
resist
resist
resist
V
V
G
cap
cap
Optional -
see text
Cutout in ground and power plane.
Route all traces away from this area.
V
= connect to VDD
G
= connect to GND
Figure 2. Typical MK2049-34 Layout
