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ST16C550CP40-F

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ST16C550
4
Rev. 5.01
Symbol Pin Signal Pin Description
40 44 48 type
SYMBOL DESCRIPTION
A0 28 31 28 I Address-0 Select Bit Internal registers address selection.
A1 27 30 27 I Address-1 Select Bit Internal registers address selection.
A2 26 29 26 I Address-2 Select Bit Internal registers address selection.
IOR 22 25 20 I Read data strobe. Its function is the same as -IOR (see -
IOR), except it is active high. Either an active -IOR or IOR
is required to transfer data from 16C550 to CPU during a
read operation. Connect to logic 0 when using -IOR.
CS0 12 14 9 I Chip Select-0. Logical 1 on this pin provides the chip select-
0 function. Connect CS0 to logic 1 if using CS1 or -CS2.
CS1 13 15 10 I Chip Select-1. Logical 1 on this pin provides the chip select-
1 function. Connect CS1 to logic 1 if using CS0 or -CS2.
-CS2 14 16 11 I Chip Select -2. Logical 0 on this pin provides the chip select-
2 function. Connect to logic 0 if using CS0 or CS1.
IOW 19 21 17 I Write data strobe. Its function is the same as -IOW (see -
IOW), but it acts as an active high input signal. Either -IOW
or IOW is required to transfer data from the CPU to
ST16C550 during a write operation. Connect to logic 0 when
using -IOW.
-AS 25 28 24 I Address Strobe. A logic 1 transition on -AS latches the state
of the chip selects and the register select bits, A0-A2. This
input is used when address and chip selects are not stable
for the duration of a read or write operation, i.e., a micropro-
cessor that needs to de-multiplex the address and data bits.
If not required, the -AS input can be permanently tied to a
logic 0.
D0-D7 1-8 2-9 43-47
2-4 I/O Data Bus (Bi-directional) - These pins are the eight bit, tri-
state data bus for transferring information to or from the
controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
GND 20 22 18 Pwr Signal and Power Ground.
ST16C550
5
Rev. 5.01
Symbol Pin Signal Pin Description
40 44 48 type
SYMBOL DESCRIPTION
-IOR 21 24 19 I Read data strobe (active low strobe). A logic 0 on this pin
transfers the contents of the ST16C550 data bus to the CPU.
Connect to logic 1 when using IOR.
-IOW 18 20 16 I Write data strobe (active low strobe). A logic 0 on this pin
transfers the contents of the CPU data bus to the addressed
internal register. Connect to logic 1 when using IOW.
INT 30 33 30 O Interrupt Request (active high). Interrupts are enabled in the
interrupt enable register (IER), and when an interrupt con-
dition exists. Interrupt conditions include: receiver errors,
available receiver buffer data, transmit buffer empty, or
when a modem status flag is detected.
-RXRDY 29 32 29 O Receive Ready. When operating in the FIFO mode, one of
two types of DMA signaling can be selected using the FIFO
control register bit-3. When operating in the ST16C450
mode, only DMA mode “0” is allowed. Mode “0” supports
single transfer DMA in which a transfer is made between
CPU bus cycles. Mode “1” supports multi-transfer DMA in
which multiple transfers are made continuously until the
receiver FIFO has been emptied. In DMA mode “0” -RXRDY
is low, when there is at least one character in the receiver
FIFO or receive holding register. In DMA mode “1”, -RXRDY
is low, when the trigger level or the time-out has been
reached.
-TXRDY 24 27 23 O Transmit Ready. When operating in the FIFO mode, one of
two types of DMA signaling can be selected using the FIFO
control register bit-3. When operating in the ST16C450
mode, only DMA mode “0” is allowed. Mode “0” supports
single transfer DMA in which a transfer is made between
CPU bus cycles. Mode “1” supports multi-transfer DMA in
which multiple transfers are made continuously until the
transmit FIFO has been filled.
-BAUDOUT 15 17 12 O Baud Rate Generator Output. This pin provides the 16X
clock of the selected data rate from the baud rate generator.
The RCLK pin must be connected externally to -BAUDOUT
when the receiver is operating at the same data rate.
ST16C550
6
Rev. 5.01
Symbol Pin Signal Pin Description
40 44 48 type
SYMBOL DESCRIPTION
-DDIS 23 26 22 O Drive Disable. This pin goes to a logic 0 when the external
CPU is reading data from the ST16C550. This signal can be
used to disable external transceivers or other logic func-
tions.
-OP1 34 38 34 O Output-1 (User Defined) - See bit-2 of modem control
register (MCR bit-2).
RESET 35 39 35 I Reset. (active high) - A logic 1 on this pin will reset the
internal registers and all the outputs. The UART transmitter
output and the receiver input will be disabled during reset
time. (See ST16C550 External Reset Conditions for initial-
ization details.)
RCLK 9 10 5 I Receive Clock Input. This pin is used as external 16X clock
input to the receiver section. External connection to -
Baudout pin is required in order to utilize the internal baud
rate generator.
-OP2 31 35 31 O Output-2 (User Defined). This pin provides the user a
general purpose output. See bit-3 modem control register
(MCR bit-3).
VCC 40 44 42 Pwr Power Supply Input.
XTAL1 16 18 14 I Crystal or External Clock Input - Functions as a crystal input
or as an external clock input. A crystal can be connected
between this pin and XTAL2 to form an internal oscillator
circuit. An external 1 MΩ resistor is required between the
XTAL1 and XTAL2 pins (see figure 3). Alternatively, an
external clock can be connected to this pin to provide
custom data rates (Programming Baud Rate Generator
section).
XTAL2 17 19 15 O Output of the Crystal Oscillator or Buffered Clock - (See also
XTAL1). Crystal oscillator output or buffered clock output.
-CD 38 42 40 I Carrier Detect (active low) - A logic 0 on this pin indicates
that a carrier has been detected by the modem.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

ST16C550CP40-F

Mfr. #:
Buy ST16C550CP40-F
Manufacturer:
MaxLinear
Description:
UART Interface IC SINGLE UART W/16 BYTE FIFO
Lifecycle:
New from this manufacturer.
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