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AD7846BP

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AD7846
Rev. G | Page 3 of 24
SPECIFICATIONS
V
DD
= +14.25 V to +15.75 V; V
SS
= −14.25 V to –15.75 V; V
CC
= +4.75 V to +5.25 V. V
OUT
loaded with 2 kΩ, 1000 pF to 0 V; V
REF+
= +5 V;
R
IN
connected to 0 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
1
J, A Versions K, B Versions Unit Test Conditions/Comments
RESOLUTION 16 16 Bits
UNIPOLAR OUTPUT V
REF−
= 0 V, V
OUT
= 0 V to +10 V
Relative Accuracy at +25°C ±12 ±4 LSB typ 1 LSB = 153 V
T
MIN
to T
MAX
±16 ±8 LSB max
Differential Nonlinearity Error ±1 ±0.5 LSB max All grades guaranteed monotonic
Gain Error at +25°C ±12 ±6 LSB typ V
OUT
load = 10 MΩ
T
MIN
to T
MAX
±16 ±16 LSB max
Offset Error at +25°C ±12 ±6 LSB typ
T
MIN
to T
MAX
±16 ±16 LSB max
Gain TC
2
±1 ±1 ppm FSR/°C typ
Offset TC
2
±1 ±1 ppm FSR/°C typ
BIPOLAR OUTPUT V
REF−
= –5 V, V
OUT
= −10 V to +10 V
Relative Accuracy at +25°C ±6 ±2 LSB typ 1 LSB = 305 V
T
MIN
to T
MAX
±8 ±4 LSB max
Differential Nonlinearity Error ±1 ±0.5 LSB max All grades guaranteed monotonic
Gain Error at +25°C ±6 ±4 LSB typ V
OUT
load = 10 MΩ
T
MIN
to T
MAX
±16 ±16 LSB max
Offset Error at +25°C ±6 ±4 LSB typ V
OUT
load = 10 MΩ
T
MIN
to T
MAX
±16 ±12 LSB max
Bipolar Zero Error at +25°C ±6 ±4 LSB typ
T
MIN
to T
MAX
±12 ±8 LSB max
Gain TC
2
±1 ±1 ppm FSR/°Ctyp
Offset TC
2
±1 ±1 ppm FSR/°Ctyp
Bipolar Zero TC
2
±1 ±1 ppm FSR/°Ctyp
REFERENCE INPUT
Input Resistance 20 20 kΩ min Resistance from V
REF+
to V
REF−
40 40 kΩ max Typically 30 kΩ
V
REF+
Range V
SS
+ 6 to V
SS
+ 6 to V min to
V
DD
− 6 V
DD
− 6 V max
V
REF−
Range V
SS
+ 6 to V
SS
+ 6 to V min to
V
DD
− 6 V
DD
− 6 V max
OUTPUT CHARACTERISTICS
Output Voltage Swing
V
SS
+ 4 to V
SS
+ 4 to
V max
V
DD
− 3 V
DD
− 3
Resistive Load 2 2 kΩ min To 0 V
Capacitive Load 1000 1000 pF max To 0 V
Output Resistance 0.3 0.3 Ω typ
Short Circuit Current ±25 ±25 mA typ To 0 V or any power supply
DIGITAL INPUTS
V
IH
(Input High Voltage) 2.4 2.4 V min
V
IL
(Input Low Voltage) 0.8 0.8 V max
I
IN
(Input Current) ±10 ±10 A max
C
IN
(Input Capacitance)
2
10 10 pF max
AD7846
Rev. G | Page 4 of 24
Parameter
1
J, A Versions K, B Versions Unit Test Conditions/Comments
DIGITAL OUTPUTS
V
OL
(Output Low Voltage) 0.4 0.4 V max I
SINK
= 1.6 mA
V
OH
(Output High Voltage) 4.0 4.0 V min I
SOURCE
= 400 A
Floating State Leakage Current ±10 ±10 A max DB0 to DB15 = 0 to V
CC
Floating State Output Capacitance
2
10 10 pF max
POWER REQUIREMENTS
3
V
DD
+11.4/+15.75 +11.4/+15.75 V min/V max
V
SS
−11.4/−15.75 −11.4/−15.75 V min/V max
V
CC
+4.75/+5.25 +4.75/+5.25 V min/V max
I
DD
5 5 mA max V
OUT
unloaded
I
SS
5 5 mA max V
OUT
unloaded
I
CC
1 1 mA max
Power Supply Sensitivity
4
1.5 1.5 LSB/V max
Power Dissipation 100 100 mW typ V
OUT
unloaded
1
Temperature ranges as follows: J, K versions: 0°C to +70°C; A, B versions: −40°C to +85°C.
2
Guaranteed by design and characterization, not production tested.
3
The AD7846 is functional with power supplies of ±12 V. See the Typical Performance Characteristics section.
4
Sensitivity of gain error, offset error, and bipolar zero error to V
DD
, V
SS
variations.
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance and are not subject to test. V
REF+
= +5 V; V
DD
= +14.25 V to +15.75 V; V
SS
= −14.25 V
to −15.75 V; V
CC
= +4.75 V to +5.25 V; R
IN
connected to 0 V, unless otherwise noted.
Table 2.
Parameter Limit at T
MIN
to T
MAX
(All Versions) Unit Test Conditions/Comments
Output Settling Time
1
6 s max To 0.006% FSR, V
OUT
loaded, V
REF−
= 0 V, typically 3.5 s
9 s max To 0.003% FSR, V
OUT
loaded, V
REF−
= –5 V, typically 6.5 s
Slew Rate 7 V/s typ
Digital-to-Analog Glitch
Impulse 70 nV-sec typ
DAC alternately loaded with 10…0000 and 01…1111,
V
OUT
unloaded
AC Feedthrough 0.5 mV p-p typ
V
REF−
= 0 V, V
REF+
= 1 V rms, 10 kHz sine wave, DAC loaded
with all 0s
Digital Feedthrough 10 nV-sec typ
DAC alternately loaded with all 1s and all 0s. CS
high
Output Noise Voltage
Density, 1 kHz to 100 kHz
50 nV/√Hz typ
Measured at V
OUT
, DAC loaded with 0111011…11,
V
REF+
= V
REF−
= 0 V
1
LDAC
= 0. Settling time does not include deglitching time of 2.5 µs (typ).
AD7846
Rev. G | Page 5 of 24
TIMING CHARACTERISTICS
V
DD
= +14.25 V to +15.75 V, V
SS
= −14.25 V to −15.75 V, V
CC
= +4.75 V to +5.25 V, unless otherwise noted.
Table 3.
Parameter
1
Limit at T
MIN
to T
MAX
(All Versions) Unit Test Conditions/Comments
t
1
0 ns min
R/W
to CS setup time
t
2
60 ns min
CS
pulse width (write cycle)
t
3
0 ns min
R/W
to CS hold time
t
4
60 ns min Data setup time
t
5
0 ns min Data hold time
t
6
2
120 ns max Data access time
t
7
3
10 ns min Bus relinquish time
60 ns max
t
8
0 ns min
CLR
setup time
t
9
70 ns min
CLR
pulse width
t
10
0 ns min
CLR
hold time
t
11
70 ns min
LDAC
pulse width
t
12
130 ns min
CS
pulse width (read cycle)
1
Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with t
R
= t
F
= 5 ns (10% to 90% of +5 V) and timed from a
voltage level of 1.6 V.
2
t
6
is measured with the load circuits of Figure 3 and Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
t
7
is defined as the time required for an output to change 0.5 V when loaded with the circuits of Figure 5 and Figure 6.
DB0
TO
DB15
5V
t
3
t
1
t
3
DATA VALIDDATA VALID
t
11
t
10
LDAC
CLR
CS
R/W
0V
5V
0V
5V
0V
5V
0V
5V
0V
t
10
t
8
t
9
t
6
t
1
t
8
t
9
t
4
t
5
t
7
t
12
t
2
0
8490-006
Figure 2. Timing Diagram
DBn
3kΩ
100pF
DGND
0
8490-002
Figure 3. Load Circuit for Access Time (t
6
)—High Z to V
OH
DBn
100pF
3kΩ
DGND
5
V
08490-003
Figure 4. Load Circuits for Bus Relinquish Time (t
6
)—High Z to V
OL
DBn
3kΩ
10pF
DGND
08490-004
Figure 5. Load Circuit for Access Time (t
7
)—High Z to V
OH
DBn
10pF
3kΩ
DGND
5
V
08490-005
Figure 6. Load Circuits for Bus Relinquish Time (t
7
)—High Z to V
OL
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AD7846BP

Mfr. #:
Buy AD7846BP
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 16-Bit VOut CMOS
Lifecycle:
New from this manufacturer.
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