NCP3102C
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10
Normal Shutdown Behavior
Normal shutdown occurs when the IC stops switching
because the input supply reaches UVLO threshold. In this
case, switching stops, the internal soft start, SS, is
discharged, and all gate pins are driven low. The switch node
enters a high impedance state and the output capacitors
discharge through the load with no ringing on the output
voltage.
External Soft--Start
The NCP3102C features an external soft start function,
which reduces inrush current and overshoot of the output
voltage. Soft start is achieved by using the internal current
source of 10 mA (typ), which charges the external integrator
capacitor of the transconductance amplifier. Figures 21
and 22 are typical soft start sequences. The sequence begins
once V
CC
surpasses its UVLO threshold. During Soft Start
as the Comp Pin rises through 400 mV, the PWM logic and
gate drives are enabled. When the feedback voltage crosses
800 mV, the EOTA will be given control to switch to its
higher regulation mode with the ability to source and sink
130 mA. In the event of an over current during the soft start,
the overcurrent logic will override the soft start sequence
and will shut down the PWM logic and both the high side and
low side gates of the switching MOSFETS.
Vcomp
0.83V
Vfb
Isource/
sink
10uA
--10uA
120uA
Normal
Start up
0.4V0.4V
SS
Enable
10uA
0.8V
Figure 21. Soft--Start I mplementation
VCC
COMP
VFB
BG
TG
BG Comparator
DAC Voltage
BG Comparator
Output
Vout
50mV
500mV
UVLO
POR
Delay
Current
Trip Set
COMP
Delay
Normal Operation
UVLO
0.9 V
4.3 V
3.4 V
Figure 22. Soft--Start Sequence
UVLO
Under Voltage Lockout (UVLO) is provided to ensure that
unexpected behavior does not occur when V
CC
is too low to
support the internal rails and power the converter. For the
NCP3102C, the UVLO is set to ensure that the IC will start
up when VCC reaches 4.0 V and shutdown when V
CC
drops
below 3.6 V. The UVLO feature permits smooth operation
from a varying 5.0 V input source.
Current Limit Protection
In case of a short circuit or overload, the low--side (LS)
FET will conduct large currents. The low--side R
DS(on)
sense
is implemented to protect from over current by comparing
the voltage at the phase node to AGND just prior to the low
side MOSFET turnoff to an internally generated fixed
voltage. If the differential phase node voltage is lower than
OC trip voltage, an overcurrent condition occurs and a
counter is initiated. If seven consecutive over current trips
are counted, the PWM logic and both HS--FET and LS--FET
are latch off. The converter will be latched off until input
power drops below the UVLO threshold. The operation of
key nodes are displayed in Figure 23 for both normal
operation and during over current conditions.