DATASHEET
9FGU0441 OCTOBER 18, 2016 1 ©2016 Integrated Device Technology, Inc.
4 O/P 1.5V PCIe Gen1-2-3 Clock Generator
w/Zo=100ohms
9FGU0441
Description
The 9FGU0441 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family with integrated output terminations
providing Zo=100. The device has 4 output enables for
clock management, 2 different spread spectrum levels in
addition to spread off and 2 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 clock generator
Output Features
4 - 100MHz Low-Power (LP) HCSL DIF pairs
w/Zo=100ohms
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 3.0ps RMS
Features/Benefits
Direct connection to 100ohm transmission lines; saves 16
resistors compared to standard PCIe devices
39mW typical power consumption; reduced thermal
concerns
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 32-pin 5x5 mm VFQFPN; minimal board
space
Block Diagram
XIN/CLKIN_25
X2
CONTROL
LOGIC
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SS Capable PLL
OSC
REF1.5
vOE(3:0)#
SCLK_3.3
vSADR
DIF3
DIF2
DIF1
DIF0
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 2 OCTOBER 18, 2016
9FGU0441 DATASHEET
Pin Configuration
SMBus Address Selection Table
Power Management Table
Power Connections
vSS_EN_tri
^CKPWRGD_PD#
GND
vOE3#
DIF3#
DIF3
GND
VDDO1.5
32 31 30 29 28 27 26 25
GNDXTAL 1
24
vOE2#
XIN/CLKIN_25 2
23
DIF2#
X2 3
22
DIF2
VDDXTAL1.5 4
21
VDDA1.5
VDDREF1.5 5
20
GNDA
vSADR/REF1.5 6
19
DIF1#
GNDREF
7
18
DIF1
GNDDIG
817vOE1#
9 10111213141516
VDDDIG1.5
SCLK_3.3
SDATA_3.3
vOE0#
DIF0
DIF0#
GND
VDDO1.5
32-pin VFQFPN, 5x5 mm, 0.5mm pitch
v prefix indicates internal 120KOhm pull down resistor
9FGU0441
^ prefix indicates internal 120KOhm pull up resistor
SADR Address
0 1101000
1 1101010
State of SADR on first application
of CKPWRGD_PD#
+ Read/Write Bit
x
x
OEx# True O/P Comp. O/P
0 X X Low Low
Hi-Z
1
1 1 0 Running Running Running
1 0 1 Low Low Low
REF
CKPWRGD_PD#
SMBus
OE bit
DIFx
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is Low.
Pin Number
VDD GND
41
57
98, 30
16, 25 15, 26
21 20 PLL Analog
REF Output
Description
XTAL Analog
Digital Power
DIF outputs
OCTOBER 18, 2016 3 4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
9FGU0441 DATASHEET
Pin Descriptions
Pin# Pin Name Type Pin Description
1 GNDXTAL GND GND for XTAL
2 XIN/CLKIN_25 IN Crystal input or Reference Clock input. Nominally 25MHz.
3 X2 OUT Crystal output.
4 VDDXTAL1.5 PWR Power supply for XTAL, nominal 1.5V
5 VDDREF1.5 PWR VDD for REF output. nominal 1.5V.
6 vSADR/REF1.5
LATCHED
I/O
Latch to select SMBus Address/1.5V LVCMOS copy of X1/REFIN pin
7 GNDREF GND Ground pin for the REF outputs.
8 GNDDIG GND Ground pin for digital circuitry
9 VDDDIG1.5 PWR 1.5V digital power (dirty power)
10 SCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant.
11 SDATA_3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant.
12 vOE0# IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
13 DIF0 OUT Differential true clock output
14 DIF0# OUT Differential Complementary clock output
15 GND GND Ground pin.
16 VDDO1.5 PWR Power supply for outputs, nominally 1.5V.
17 vOE1# IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
18 DIF1 OUT Differential true clock output
19 DIF1# OUT Differential Complementary clock output
20 GNDA GND Ground pin for the PLL core.
21 VDDA1.5 PWR 1.5V power for the PLL core.
22 DIF2 OUT Differential true clock output
23 DIF2# OUT Differential Complementary clock output
24 vOE2# IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
25 VDDO1.5 PWR Power supply for outputs, nominally 1.5V.
26 GND GND Ground pin.
27 DIF3 OUT Differential true clock output
28 DIF3# OUT Differential Complementary clock output
29 vOE3# IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
30 GND GND Ground pin.
31 ^CKPWRGD_PD# IN
Input notifies device to sample latched inputs and start up on first high assertion.
Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
32 vSS_EN_tri LATCHED IN
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off

9FGU0441AKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 4-output 1.5 V PCIe Gen1-2-3 Clock Gen
Lifecycle:
New from this manufacturer.
Delivery:
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