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9FGU0441AKILF

P1-P3P4-P6P7-P9P10-P12P13-P15
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 4 OCTOBER 18, 2016
9FGU0441 DATASHEET
Test Loads
Alternate Terminations
REF Output
33
REF Output Test Load
5pF
Zo = 50 ohms
Driving LVDS inputs
Receiver has
termination
Receiver does not
have termination
R7a, R7b 10K ohm 140 ohm
R8a, R8b 5.6K ohm 75 ohm
Cc 0.1 uF 0.1 uF
Vcm 1.2 volts 1.2 volts
Component
Value
Note
Rs
Device
Rs
Zo
Driving LVDS
Cc
Cc
R7a R7b
R8a
R8b
3.3V
LVDS Clock
input
OCTOBER 18, 2016 5 4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
9FGU0441 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGU0441. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Electrical Characteristics–Current Consumption
Electrical Characteristics–DIF Output Duty Cycle, Jitter, and Skew Characteristics
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
Supply Voltage VDDxx Applies to all VDD pins -0.5 2 V 1,2
Input Voltage V
IN
-0.5 V
DD
+0.5V V 1,3
Input High Voltage, SMBus V
IHSMB
SMBus clock and data pins 3.3V V 1
Storage Temperature Ts -65 150 °C 1
Junction Temperature Tj 125 °C 1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
I
DDAOP
VDDA, All outputs active @100MHz 6.2 9 mA
I
DDOP
All VDD, except VDDA and VDDIO, All outputs
active @100MHz
21 27 mA
I
DDAPD
VDDA, DIF outputs off, REF output running 0.4 1 mA 2
I
DDPD
All VDD, except VDDA and VDDIO,
DIF outputs off, REF output running
4.5 6.5 mA 2
I
DDAPD
VDDA, all outputs off 0.4 1 mA
I
DDPD
All VDD, except VDDA and VDDIO, all outputs off 0.4 1 mA
1
Guaranteed by design and characterization, not 100% tested in production.
2
This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)
Operating Supply Current
Wake-on-LAN Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '1')
Powerdown Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '0')
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Duty Cycle t
DC
Measured differentially, PLL Mode 45 50 55 % 1,2
Skew, Output to Output t
sk3
Averaging on, V
T
= 50% 32 50 ps 1
Jitter, Cycle to cycle t
jcyc-cyc
16 50 ps 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 6 OCTOBER 18, 2016
9FGU0441 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Supply Voltage VDDxx
Supply voltage for core, analog and single-ended
LVCMOS outputs
1.425 1.5 1.575 V
Comercial range 0 25 70 °C
Industrial range -40 25 85 °C
Input High Voltage V
IH
Single-ended inputs, except SMBus 0.75 V
DD
V
DD
+ 0.3 V
Input Mid Voltage V
IM
Single-ended tri-level inputs ('_tri' suffix) 0.4 V
DD
0.5 V
DD
0.6 V
DD
V
Input Low Voltage V
IL
Single-ended inputs, except SMBus -0.3 0.25 V
DD
V
Output High Voltage V
IH
Single-ended outputs, except SMBus. I
OH
= -2mA V
DD
-0.45 V
Output Low Voltage V
IL
Single-ended outputs, except SMBus. I
OL
= -2mA 0.45 V
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA
Input Frequency F
in
XTAL, or X1 input 23 25 27 MHz
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
OU
T
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1.8 ms 1,2
SS Modulation Frequency f
MOD
Triangular Modulation 30 31.6 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1 3 clocks 1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of single-ended control inputs 5 ns 2
Trise t
R
Rise time of single-ended control inputs 5 ns 2
SMBus Input Low Voltage V
ILSMB
0.6 V
SMBus Input High Voltage V
IHSMB
V
DDSMB
= 3.3V, see note 4 for V
DDSMB
< 3.3V 2.1 3.3 V 4
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V
SMBus Sink Current I
PULLUP
@ V
OL
4mA
Nominal Bus Voltage V
DDSMB
1.425 3.3 V
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 400 kHz 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
Input Current
Ambient Operating
Temperature
T
AMB
Capacitance
3
Time from deassertion until out
p
uts are >200 mV
4
For V
DDSMB
< 3.3V, V
IHSMB
>= 0.8xV
DDSMB
P1-P3P4-P6P7-P9P10-P12P13-P15

9FGU0441AKILF

Mfr. #:
Buy 9FGU0441AKILF
Manufacturer:
IDT
Description:
Clock Generators & Support Products 4-output 1.5 V PCIe Gen1-2-3 Clock Gen
Lifecycle:
New from this manufacturer.
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