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IX2R11S3T/R
P1-P3
P4-P6
P7-P9
P10-P12
P13-P13
10
IX2R1
1
IXYS reserves the right to change limits, test conditions, and dimensions.
Figure 25
Figure 24
Quiescent
Supply Curr
ents vs.
Supply Volt
ages
V
INL
, V
INH
= 0V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0
5
10
15
20
25
30
35
40
V
CL
, V
CH
, V
DD
Supply Vol
tage (
V)
Supply Current (mA, uA)
I
CL
(mA
)
I
CH
(mA
)
I
DD
(uA)
Figure 26
LIN, HI
N Input Bi
as Current vs.
V
DD
Supply Voltage
0
2
4
6
8
10
12
14
16
18
20
0
5
10
15
20
25
V
DD
Voltage (V)
Input Bias Current (uA)
Figure 27
Figure 29
Figure 28
ENAB
LE Shutdown Delay vs. Temperature
V
DD
, V
CL
, V
CH
= 15V
0
20
40
60
80
100
120
140
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (C)
ENABLE Shutdown Delay (ns)
Low side
High si
de
Enable Threshold vs. V
DD
Logic Supply
Voltage
Active Low Enable
0
2
4
6
8
10
12
14
16
18
5
1
01
52
02
5
V
DD
Supply Volt
age (V)
ENABLE Threshold (V)
Postive Going
Outputs
Disabled
Negativ
e Going
Outputs Enabled
ENABLE Shut Off Delay vs. V
DD
Supply Voltage
60
70
80
90
100
110
120
130
0
5
10
15
20
25
V
DD
Supply Voltage (V)
Shut Down Delay (ns)
Low Side
High Si
de
V
CL
= 10V
V
CH
= 10V
V
CL
= 18V
V
CH
= 18V
V
CL
= 25V
V
CH
= 25,35V
V
CL
= 35V
Quiescent Supply Current vs. Temperature
V
DD
,V
CL
,V
CH
= 15V V
INL
, V
INH
= 0V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
-100
-5
0
0
50
100
150
Temperature (C)
Quiescent Supply Current
V
CH
(mA)
V
CL
(mA)
V
DD
(uA)
11
IX2R1
1
© 2007 IXYS CORPORATION All rights reserved
Figure 33
Figure 32
Figure 30
Figure 31
High Level Ouput V
oltage vs. Supply Voltage
V
HLGO
/ V
HHGO
= V
CL
- V
LGO
/ V
CH
- V
HGO
I
OUT =
20mA
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
5
1
01
52
02
53
03
5
V
CL
, V
CH
(V)
High Level Ouput (V)
Low Level Output Volt
age vs. Supply Voltage
V
LLGO
/ V
LHGO
= V
LGO
/ V
HGO
I
O
= 20mA
0
0.01
0.02
0.03
0.04
0.05
0.06
5
1
01
52
02
53
03
5
V
CL
, V
CH
(V)
Low Level Output (V)
Under Voltage Lock Out
vs. Temperature
Negative Going Trip Point
0
2
4
6
8
10
12
-100
-50
0
50
100
150
Temperature (C)
Under Voltage Trip Point (V)
V
CH
V
CL
Under Volt
age Lock Out vs.
Temperatur
e
Po
sitive G
oing
Trip P
oint
0
2
4
6
8
10
12
-100
-50
0
50
100
150
Temperat
ure (C)
Under Voltage Trip Point (V)
V
CH
V
CL
Figure 34
Figure 35
Output Source Current vs. Supp
ly Voltage
0
1
2
3
4
5
6
0
5
10
1
5
20
25
30
35
40
V
CL
, V
CH
Supply Voltage (V)
Ouput Source Current (A)
Output Sink Current
vs. Supply Voltage
-6
-5
-4
-3
-2
-1
0
0
5
10
15
20
25
3
0
35
40
V
CL
, V
CH
Supply Voltage (V)\
Ouput Sink Current (A)
12
IX2R1
1
IXYS reserves the right to change limits, test conditions, and dimensions.
Figure 36
Figure 37
Figure 38
Output Sourcing Current vs.
Tem
per
ature
V
DD
, V
CL
, V
CH
= 15V
0
0.5
1
1.5
2
2.5
3
-100
-50
0
50
100
150
Temperature (
C)
Source Output Current (A)
Output Si
nking Curr
ent vs.
Tem
per
ture
V
DD
, V
CL
, V
CH
= 15V
0
0.5
1
1.5
2
2.5
-100
-50
0
50
100
150
Temperatur
e (C)
Output Sink Current (A)
Offset
Leakage Current vs
. High Side Offs
et Voltage
0
20
40
60
80
100
120
0
100
200
300
400
500
600
700
High Side Off
set Voltag
e (V)
Leakage Current (uA)
Figure 39
Off
set Leakage Curr
ent vs.
Tem
perat
ure
High Side Off
set Vol
tage
= 600V
90
92
94
96
98
100
102
104
106
-100
-50
0
50
100
150
Tem
per
atur
e (C)
Offset Leakage Current (uA)
P1-P3
P4-P6
P7-P9
P10-P12
P13-P13
IX2R11S3T/R
Mfr. #:
Buy IX2R11S3T/R
Manufacturer:
Description:
IC DRVR HALF BRIDGE 2A 16-SOIC
Lifecycle:
New from this manufacturer.
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