SSL4120T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Objective data sheet Rev. 1 — 21 June 2012 13 of 47
NXP Semiconductors
SSL4120T
Resonant power supply control IC with PFC
Figure 6 shows the operation of the restart timer. Normally C
prot
is discharged to 0 V.
When a restart is requested, C
prot
is quickly charged to the upper switching level
V
u(RCPROT)
. Then the RCPROT pin becomes high ohmic and C
prot
discharges through
R
prot
. The restart time has elapsed when V
RCPROT
reaches the lower switching level
V
l(RCPROT)
(typ. 0.5 V). The IC then restarts and C
prot
is discharged.
7.5.3 Fast shut-down reset (pin SNSMAINS)
The latched Protection shut-down state will be reset when V
SUPIC
and V
SUPHV
drop below
their respective reset levels, V
rst(SUPIC)
and V
rst(SUPHV)
. Typically, the PFC boost capacitor,
C
boost
, will need to discharge before V
SUPIC
and V
SUPHV
drop below their reset levels,
which can take a long time.
Fast shut-down reset facilitates a faster reset. When the mains supply is interrupted, the
voltage on pin SNSMAINS will fall. As soon as V
SNSMAINS
falls below V
rst(SNSMAINS)
and
subsequently rises again by a hysteresis value, the IC will leave the Protection shut-down
state. The boost capacitor C
boost
does not need to be discharged to initiate a new start-up.
The Protection shut-down state can also be ended by pulling down the enable input (pin
SSHBC/EN).
7.5.4 Output overvoltage protection (pin SNSOUT)
The SSL4120T outputs are provided with overvoltage protection (OVP-output; see
Section 7.9). The output voltage can be measured via the auxiliary winding of the
resonant transformer. This voltage can be sensed at the SNSOUT pin via an external
rectifier and resistive divider. An overvoltage is detected when the SNSOUT voltage
exceeds V
ovp(SNSOUT)
(typ. 3.5 V). Once an overvoltage has been detected, the
SSL4120T will go to the Protection shut-down state.
Additional external protection circuits, such as an external overtemperature protection
circuit, can be connected to this pin. They should be connected to pin SNSOUT via a
diode so that the error condition will trigger an OVP event.
7.5.5 Output undervoltage protection (pin SNSOUT)
In applications where the SSL4120T is supplied from the auxiliary winding of the HBC
transformer, a SUPIC undervoltage protection event (UVP-SUPIC) will be triggered
automatically when an error condition results in a drop in the output voltage.
Fig 6. Operation of the restart timer
passed
0
no
yes
V
u(RCPROT)
V
l(RCPROT)
Restart request
014aaa854
V
RCPROT
t
Restart time
SSL4120T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Objective data sheet Rev. 1 — 21 June 2012 14 of 47
NXP Semiconductors
SSL4120T
Resonant power supply control IC with PFC
In applications where the SSL4120T is supplied from a separate DC source (e.g. a
standby supply), the SSL4120T will not automatically stop switching if an error condition
causes the output voltage to fall. For this reason, the SSL4120T outputs are provided with
undervoltage protection (UVP output; see Section 7.9
). A UVP output event will restart the
IC if V
SNSOUT
drops below V
uvp(SNSOUT)
(typ. 2.3 V).
During start-up, the output voltage will be below V
uvp(SNSOUT)
for a time. This should not
be considered an error condition provided it doesn’t last longer than expected. For this
reason, the protection timer is started as soon as V
SNSOUT
drops below V
uvp(SNSOUT)
. The
Restart state is activated if the UVP output event is still active once the protection time has
expired.
7.5.6 OverTemperature Protection (OTP)
Accurate internal overtemperature protection is provided in the SSL4120T. When the
junction temperature exceeds the overtemperature protection activation temperature, T
otp
(typ. 150 °C), the IC will go to the Thermal hold state. The SSL4120T will exit the Thermal
hold state when the temperature falls again, to around 10 °C below T
otp
.
7.6 Burst mode operation (pin SNSOUT)
The HBC and PFC controllers can be operated in Burst mode. In Burst mode the
controllers will be on for a period, then off for a period. Burst mode operation increases
efficiency under low-load conditions.
A low-load condition can be detected using a simple external circuit that makes use of the
information from the feedback loop or from the average primary current. The detection
circuit can pull down pin SNSOUT to pause operation of the SSL4120T for a burst-off
time. Both controllers, or only the HBC controller, can be paused during the burst-off time:
Burst-off level for HBC, V
burst(HBC)
(typ. 1 V).
When V
SNSOUT
drops below V
burst(HBC)
, operation of the HBC controller will be
suspended. Both the high-side and the low-side power switches will be off. The PFC
continues to operate normally. When V
SNSOUT
rises above V
burst(HBC)
again, the HBC
controller will resume normal operation, without executing a soft start sequence.
Burst-off level for PFC, V
burst(PFC)
(typ. 0.4 V).
When V
SNSOUT
drops below V
burst(PFC)
, operation of the PFC controller will also be
suspended (the HBC will have been paused already). When V
SNSOUT
rises above
V
burst(PFC)
again, the PFC controller will resume normal operation via a PFC soft start
(see Section 7.7.6
).
To ensure Burst mode is not activated before the output voltage becomes valid, a current
from the SNSOUT pin (typ. 100 μA) will hold V
SNSOUT
at V
pu(SNSOUT)
, which is above both
burst levels. The resistance between the SNSOUT pin and ground should therefore be
greater than 20 kΩ.
SSL4120T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Objective data sheet Rev. 1 — 21 June 2012 15 of 47
NXP Semiconductors
SSL4120T
Resonant power supply control IC with PFC
7.7 PFC controller
The PFC controller converts the rectified universal mains voltage into an accurately
regulated boost voltage of 400 V (DC). It operates in quasi-resonant or discontinuous
conduction mode and is controlled via an on-time control system. The resulting mains
harmonic current emissions of a typical application will easily meet the class-D MHR
requirements.
The PFC controller uses valley switching to minimize losses. A primary stroke is only
started once the previous secondary stroke has ended and the voltage across the PFC
MOSFET has reached a minimum value.
7.7.1 PFC gate driver (pin GATEPFC)
The circuit driving the gate of the power MOSFET has a high current sourcing capability
I
source(GATEPFC)
(typ. 500 mA) and a high current sink capability I
sink(GATEPFC)
(typ. 1.2 A).
This permits fast turn-on and turn-off of the power MOSFET to ensure efficient operation.
The driver is supplied from the regulated SUPREG supply.
7.7.2 PFC on-time control
The PFC operates under on-time control. The on-time of the PFC MOSFET is determined
by:
The error amplifier and the loop compensation via the voltage on pin COMPPFC
At V
ton(COMPPFC)zero
(typ. 3.5 V), the on-time is reduced to zero. At V
ton(COMPPFC)max
the on-time is at a maximum
Mains compensation via the voltage on pin SNSMAINS
7.7.2.1 PFC error amplifier (pins COMPPFC and SNSBOOST)
The boost voltage is divided via a high-ohmic resistive divider. It is fed to the SNSBOOST
pin. The transconductance error amplifier, which compares the SNSBOOST voltage with
an accurate trimmed reference voltage V
reg(SNSBOOST)
, is connected to this pin. The
output current is filtered by the external loop compensation network at the COMPPFC pin.
In a typical application, the bandwidth of the regulation loop is set by a resistor and two
capacitors.
The COMPPFC voltage is clamped at a maximum of V
clamp(COMPPFC)
. This avoids a long
recovery time in the event that the boost voltage rises above the regulation level for a
period of time.
7.7.2.2 PFC mains compensation (pin SNSMAINS)
The mathematical equation for the transfer function of a power factor corrector contains
the square of the mains input voltage. In a typical application, this will result in a low
bandwidth for low mains input voltages, while at high mains input voltages the MHR
requirements may be hard to meet.
The SSL4120T contains a correction circuit to compensate for this effect. The average
mains voltage is measured via the SNSMAINS pin and this information is fed to an
internal compensation circuit. Figure 7
illustrates the relationship between the SNSMAINS
voltage, the COMPPFC voltage, and the on-time. This compensation makes it is possible

SSL4120T/1,518

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NXP Semiconductors
Description:
Display Drivers & Controllers Resonant powersupply controller with PFC
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