19 of 48 October 3, 2011
IDT 89HPES48H12 Data Sheet
Thermal Considerations
This section describes thermal considerations for the PES48H12 (35mm
2
FCBGA1156 package). The data in Table 17 below contains information
that is relevant to the thermal performance of the PES48H12 switch.
Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the T
J(max)
value
specified in Table 17. Consequently, the effective junction to ambient thermal resistance (
θ
JA
) for the worst case scenario must be
maintained below the value determined by the formula:
θ
JA
= (T
J(max)
- T
A(max)
)/P
Given that the values of T
J(max)
, T
A(max)
, and P are known, the value of desired θ
JA
becomes a known entity to the system designer. How to
achieve the desired
θ
JA
is left up to the board or system designer, but in general, it can be achieved by adding the effects of θ
JC
(value
provided in Table 17), thermal resistance of the chosen adhesive (
θ
CS
), that of the heat sink (θ
SA
), amount of airflow, and properties of the
circuit board (number of layers and size of the board). As a general guideline, this device will not need a heat sink if the board has 10 or
more layers AND the board size is larger than 4"x12" AND airflow in excess of 1 m/s is available. It is strongly recommended that users
perform their own thermal analysis for their own board and system design scenarios.
Symbol Parameter Value Units Conditions
T
J(max)
Junction Temperature 125
o
C Maximum
T
A(max)
Ambient Temperature 70
o
C Maximum for commercial-rated products
θ
JA(effective)
Effective Thermal Resistance, Junction-to-Ambient
12.6
o
C/W Zero air flow
6.4
o
C/W 1 m/S air flow
5.4
o
C/W 2 m/S air flow
θ
JB
Thermal Resistance, Junction-to-Board 2.1
o
C/W
θ
JC
Thermal Resistance, Junction-to-Case 0.1
o
C/W
P Power Dissipation of the Device 6.82 Watts Maximum
Table 17 Thermal Specifications for PES48H12, 35x35mm FCBGA1156 Package
20 of 48 October 3, 2011
IDT 89HPES48H12 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 13.
Note: See Table 8, Pin Characteristics, for a complete I/O listing.
I/O Type Parameter Description Min
1
Typ
1
Max
1
Unit Conditions
Serial Link PCIe Transmit
V
TX-DIFFp-p
Differential peak-to-peak output voltage 800 1200 mV
V
TX-DE-RATIO
De-emphasized differential output voltage -3 -4 dB
V
TX-DC-CM
DC Common mode voltage -0.1 1 3.7 V
V
TX-CM-ACP
RMS AC peak common mode output volt-
age
20 mV
V
TX-CM-DC-
active-idle-delta
Abs delta of DC common mode voltage
between L0 and idle
100 mV
V
TX-CM-DC-line-
delta
Abs delta of DC common mode voltage
between D+ and D-
25 mV
V
TX-Idle-DiffP
Electrical idle diff peak output 20 mV
V
TX-RCV-Detect
Voltage change during receiver detection 600 mV
RL
TX-DIFF
Transmitter Differential Return loss 12 dB
RL
TX-CM
Transmitter Common Mode Return loss 6 dB
Z
TX-DEFF-DC
DC Differential TX impedance 80 100 120 Ω
Z
OSE
Single ended TX Impedance 40 50 60 Ω
Transmitter Eye
Diagram
TX Eye Height (De-emphasized bits) 505 650 mV
Transmitter Eye
Diagram
TX Eye Height (Transition bits) 800 950 mV
PCIe Receive
V
RX-DIFFp-p
Differential input voltage (peak-to-peak) 175 1200 mV
V
RX-CM-AC
Receiver common-mode voltage for AC
coupling
150 mV
RL
RX-DIFF
Receiver Differential Return Loss 15 dB
RL
RX-CM
Receiver Common Mode Return Loss 6 dB
Z
RX-DIFF-DC
Differential input impedance (DC) 80 100 120 Ω
Z
RX-COMM-DC
Single-ended input impedance 40 50 60 Ω
Z
RX-COMM-HIGH-
Z-DC
Powered down input common mode
impedance (DC)
200k 350k Ω
V
RX-IDLE-DET-
DIFFp-p
Electrical idle detect threshold 65 175 mV
PCIe REFCLK
C
IN
Input Capacitance 1.5 pF
Table 18 DC Electrical Characteristics (Part 1 of 2)
21 of 48 October 3, 2011
IDT 89HPES48H12 Data Sheet
Other I/Os
LOW Drive
Output
I
OL
—2.5—mA V
OL
= 0.4v
I
OH
—-5.5—mA V
OH
= 1.5V
High Drive
Output
I
OL
12.0 mA V
OL
= 0.4v
I
OH
—-20.0—mA V
OH
= 1.5V
Schmitt Trig-
ger Input
(STI)
V
IL
-0.3 0.8 V
V
IH
2.0 V
DD
IO +
0.5
V—
Input V
IL
-0.3 0.8 V
V
IH
2.0 V
DD
IO +
0.5
V—
Capacitance C
IN
——8.5pF
Leakage Inputs + 10 μAV
DD
I/O (max)
I/O
LEAK W/O
Pull-ups/downs
——+
10 μAV
DD
I/O (max)
I/O
LEAK WITH
Pull-ups/downs
——+
80 μAV
DD
I/O (max)
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a.
I/O Type Parameter Description Min
1
Typ
1
Max
1
Unit Conditions
Table 18 DC Electrical Characteristics (Part 2 of 2)

89HPES48H12ZABL

Mfr. #:
Manufacturer:
IDT
Description:
PCI Interface IC PCIE 64-LANE 16 PORT SWIT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union