9 of 48 October 3, 2011
IDT 89HPES48H12 Data Sheet
P01MERGEN I Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low internally via
a 251K ohm resistor.
When this pin is low, port 0 is merged with port 1 to form a single x8 port. The Serdes
lanes associated with port 1 become lanes 4 through 7 of port 0. When this pin is
high, port 0 and port 1 are not merged, and each operates as a single x4 port.
P23MERGEN I Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled low internally via
a 251K ohm resistor.
When this pin is low, port 2 is merged with port 3 to form a single x8 port. The Serdes
lanes associated with port 3 become lanes 4 through 7 of port 2. When this pin is
high, port 2 and port 3 are not merged, and each operates as a single x4 port.
P45MERGEN I Port 4 and 5 Merge. P45MERGEN is an active low signal. It is pulled low internally via
a 251K ohm resistor.
When this pin is low, port 4 is merged with port 5 to form a single x8 port. The Serdes
lanes associated with port 5 become lanes 4 through 7 of port 4. When this pin is
high, port 4 and port 5 are not merged, and each operates as a single x4 port.
P67MERGEN I Port 6 and 7 Merge. P67MERGEN is an active low signal. It is pulled low internally via
a 251K ohm resistor.
When this pin is low, port 6 is merged with port 7 to form a single x8 port. The Serdes
lanes associated with port 7 become lanes 4 through 7 of port 6. When this pin is
high, port 6 and port 7 are not merged, and each operates as a single x4 port.
P89MERGEN I Port 8 and 9 Merge. P89MERGEN is an active low signal. It is pulled low internally via
a 251K ohm resistor.
When this pin is low, port 8 is merged with port 9 to form a single x8 port. The Serdes
lanes associated with port 9 become lanes 4 through 7 of port 8. When this pin is
high, port 8 and port 9 are not merged, and each operates as a single x4 port.
P1011MERGEN I Port 10 and 11 Merge. P67MERGEN is an active low signal. It is pulled low internally
via a 251K ohm resistor.
When this pin is low, port 10 is merged with port 11 to form a single x8 port. The
Serdes lanes associated with port 11 become lanes 4 through 7 of port 10. When this
pin is high, port 10 and port 11 are not merged, and each operates as a single x4 port.
PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside PES48H12 and ini-
tiates a PCI Express fundamental reset.
RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset,
PES48H12 executes the reset procedure and remains in a reset state with the Master
and Slave SMBuses active. This allows software to read and write registers internal to
the device before normal device operation begins. The device exits the reset state
when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master.
SWMODE[3:0] I Switch Mode. These configuration pins determine the PES48H12 switch operating
mode. These pins should be static and not change following the negation of PERSTN.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - Normal switch mode with upstream port failover (port 0 selected as the
upstream port)
0x9 - Normal switch mode with upstream port failover (port 2 selected as the
upstream port)
0xA - Normal switch mode with Serial EEPROM initialization and upstream port
failover (port 0 selected as the upstream port)
0xB - Normal switch mode with Serial EEPROM initialization and upstream port
failover (port 2 selected as the upstream port)
0xC through 0xF - Reserved
Signal Type Name/Description
Table 5 System Pins (Part 2 of 2)
