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ADN8810ACPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Data Sheet ADN8810
Rev. B | Page 3 of 16
SPECIFICATIONS
AVDD = DVDD = 5 V, PVDD = 3.3 V, AVSS = DVSS = DGND = 0 V, TA = 25°C, covering IOUT from 2% IFS to 100% IFS, unless
otherwise noted.
Table 1. Electrical Characteristics
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DC PERFORMANCE
Resolution N 12 Bits
Relative Accuracy INL ± 4 LSB
Differential Nonlinearity DNL ± 0.75 LSB
Offset 4 8 LSB
Offset Drift R
SN
= 1.6 Ω; I
OUT
= 127 mA 15 ppm/°C
Gain Error 1 %FS
REFERENCE INPUT
Reference Input Voltage V
REF
3.9 4.096 4.3 V
Input Current 1 µA
Bandwidth BW
REF
2 MHz
ANALOG OUTPUT
Output Current Change vs. Output
Voltage Change
∆I
OUT
/∆V
OUT
V
OUT
= 0.7 V to 2.0 V 100 400 ppm/V
Maximum Output Current I
MAX
R
SN1
= 1.37 Ω 300 mA
Output Compliance Voltage V
COMP
−40°C to +85°C; I
FS
=300 mA 2.0 2.5 V
AC PERFORMANCE
Settling Time
τ
S
3 µs
Bandwidth BW 5 MHz
Current Noise Density at 10 kHz i
N
I
FS
= 250 mA 7.5
nA/
√
Hz
I
FS
= 100 mA 3
nA/
√
Hz
I
FS
= 50 mA 1.5
nA/
√
Hz
Standby Recovery 6 µs
POWER SUPPLY
1
Power Supply Voltage
DVDD
3.0
5
5.5
V
AVDD 4.5 5 5.5 V
PVDD 3.0 3.3 5.5 V
Power Supply Rejection Ratio PSRR AVDD = 4.5 V to 5.5 V; R
SN
= 20 Ω 0.4 5 µA/V
PVDD = 3.0 V to 3.6 V; R
SN
= 20 Ω 0.4 5 µA/V
Supply Current I
DVDD
I
O
= 0 mA,
SB
= DVDD
11 50 µA
I
AVDD
I
O
= 0 mA,
SB
= DVDD
1 2 mA
I
PVDD
I
O
= 0 mA,
SB
= DVDD
3 mA
I
AVDD
SB
= 0 V
1 mA
I
PVDD
SB
= 0 V
0.33 mA
FAULT DETECTION
Load Open Threshold PVDD − 0.6 V
Load Short Threshold AVSS + 0.2 V
FAULT Logic Output V
OH
DVDD = 5.0 V 4.5 V
V
OL
DVDD = 5.0 V 0.5 V
ADN8810 Data Sheet
Rev. B | Page 4 of 16
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
LOGIC INPUTS
Input Leakage Current I
IL
1 µA
Input Low Voltage V
IL
DVDD = 3.0 V 0.5 V
DVDD = 5 V 0.8 V
Input High Voltage
V
IH
DVDD = 3.0 V
2.4
V
DVDD = 5 V 4 V
INTERFACE TIMING
2
Clock Frequency
f
CLK
12.5
MHz
RESET
Pulsewidth
t
11
40 ns
1
With respect to AVSS.
2
See the Timing Characteristics section for timing specifications.
Data Sheet ADN8810
Rev. B | Page 5 of 16
TIMING CHARACTERISTICS
Table 2. Timing Characteristics
1, 2
Parameter Description Min Typ Max Unit
f
CLK
SCLK Frequency 12.5 MHz
t
1
SCLK Cycle Time 80 ns
t
2
SCLK Width High 40 ns
t
3
SCLK Width Low 40 ns
t
4
CS
Low to SCLK High Setup
15 ns
t
5
CS
High to SCLK High Setup
15 ns
t
6
SCLK High to
CS
Low Hold
35 ns
t
7
SCLK High to
CS
High Hold
20 ns
t
8
Data Setup 15 ns
t
9
Data Hold 2 ns
t
10
CS
High Pulsewidth
30 ns
t
11
RESET
Pulsewidth
40 ns
t
12
CS
High to
RESET
Low Hold
30 ns
1
Guaranteed by design. Not production tested.
2
Sample tested during initial release and after any redesign or process change that may affect these parameters. All input signals are measured with tr = tf = 5 ns (10%
to 90% of DVDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
SCLK
C S
SDI
t
6
t
4
t
3
t
2
t
7
t
5
t
1
t
10
t
8
t
9
A3*
A2
t
12
t
11
A1 A0 D11 D10 D0
RESET
* ADDRESS BIT A3 MUST BE LOGIC LOW
03195-0-002
Figure 2. Timing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ADN8810ACPZ

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