ADF5904 Data Sheet
Rev. A | Page 6 of 15
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
GND
23
RX3_RF
22
GND
21
AV
DD
20
GND
19
RX4_RF
18
GND
17
RX4_O
1
2
3
4
5
6
7
8
GND
RX1_RF
GND
AV
DD
GND
RX2_RF
GND
RX2_O
9
10
1
1
12
13
14
15
16
RX2_OB
LE
CLK
D
ATA
CE
DOUT
ATEST
RX4_OB
32
31
30
29
28
27
26
25
RX1_O
RX1_OB
GND
LO_IN
GND
AV
DD
RX3_OB
RX3_O
T
O
P VIEW
(Not to Scale)
ADF5904
NOTES
1. THE LFCSP
HAS AN EXPOSED PAD
TH
AT MUST BE CONNECTED TO GND.
12885-004
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 3, 5, 7, 18, 20,
22, 24, 28, 30
GND Ground Pins.
2 RX1_RF Channel 1 RF Input.
4, 21, 27 AV
DD
Analog Power Supply. The supply range is 3.3 V ± 5%. Place decoupling capacitors (0.1 µF, 1 nF, and 10 pF)
to the ground plane as close as possible to this pin.
6 RX2_RF Channel 2 RF Input.
8 RX2_O Channel 2 Baseband Output.
9 RX2_OB Channel 2 Complementary Baseband Output.
10 LE Load Enable, CMOS Input. When LE goes high, data stored in the shift registers is loaded into one of the
four latches; the control bits select the latch.
11 CLK Serial Clock Input. This serial clock clocks in the serial data to the registers. Data latches into the 32-bit
shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 DATA Serial Data Input. The serial data loads MSB first and the two LSBs are the control bits.
This input is a high impedance CMOS input.
13 CE Chip Enable. A logic low on this pin powers down the device.
15 ATEST Analog Test Output
16 RX4_OB Channel 4 Complementary Baseband Output.
17 RX4_O Channel 4 Baseband Output.
19 RX4_RF Channel 4 RF Input.
23 RX3_RF Channel 3 RF Input.
25 RX3_O Channel 3 Baseband Output.
26 RX3_OB Channel 3 Complementary Baseband Output.
29 LO_IN Local Oscillator Input.
31 RX1_OB Channel 1 Complementary Baseband Output.
32 RX1_O Channel 1 Baseband Output.
EPAD Exposed Pad. The LFCSP has an exposed pad that must connect to GND.