LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5V,
3.3V LVPECL/ECL FANOUT BUFFER
ICS853031
IIDT
™
/ ICS
™
1-TO-9, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 1 ICS853031AY REV. C AUGUST 12, 2008
GENERAL DESCRIPTION
The ICS853031 is a low skew, high performance
1-to-9 Differential-to-2.5V/3.3V LVPECL/ECL
Fanout Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
IDT. The ICS853031 has two selectable clock in-
puts. The CLK, nCLK pair can accept most standard differen-
tial input levels. The PCLK, nPCLK pair can accept LVPECL,
LVDS, CML, or SSTL input levels. The clock enable is inter-
nally synchronized to eliminate runt pulses on the outputs dur-
ing asynchronous assertion/deassertion of the clock enable
pin.
Guaranteed output skew and part-to-part skew characteristics
make the ICS853031 ideal for high performance workstation and
server applications.
HiPerClockS™
ICS
FEATURES
• Nine differential 2.5V/3.3V LVPECL/ECL outputs
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL,
• PCLK, nPCLK supports the following input types:
LVPECL, LVDS, CML, SSTL
• Output frequency: 1.6GHz (typical)
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to 3.3V LVPECL levels with resistor bias on nCLK or
nPCLK inputs
• Output skew: 20ps (typical)
• Part-to-part skew: 75ps (typical)
• Propagation delay: 875ps (typical)
• LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.465V, V
EE
= 0V
• ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -2.375V to -3.465V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
compliant packages
BLOCK DIAGRAM
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
CCO
Q3
nQ3
Q4
nQ4
Q5
nQ5
V
CCO
ICS853031
Vcco
Q6
nQ6
Q7
nQ7
Q8
nQ8
Vcco
VCCO
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
CCO
VCC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
V
EE
CLK_EN
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
CLK
nCLK
PCLK
nPCLK
D
Q
LE
CLK_EN
CLK_SEL
0
1
PIN ASSIGNMENT
