IDT
/ ICS
1-TO-9, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 13 ICS853031AY REV. C AUGUST 12, 2008
ICS853031
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion.
Figures 6A and 6B
show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process varia-
tions.
TERMINATION FOR 3.3V LVPECL OUTPUTS
V
CC
- 2V
50Ω 50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT
FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω 125Ω
84Ω 84Ω
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
FIGURE 6B. LVPECL OUTPUT TERMINATIONFIGURE 6A. LVPECL OUTPUT TERMINATION
IDT
/ ICS
1-TO-9, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 14 ICS853031AY REV. C AUGUST 12, 2008
ICS853031
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION SCHEMATIC EXAMPLE
R5
50
R2
82.5
nQ8
+
-
Zo = 50 Ohm
Zo = 50 Ohm
Q8
R8
50
(U1-32)
Zo = 50 Ohm
3.3V
VCCO
C1
0.1uF
C6
0.1uF
(U1-17)
Zo = 50 Ohm
R10
50
VCC = 3.3V
CLK_SEL
Optional
Y-Termination
R9
50
+
-
Zo = 50 Ohm
C3
0.1uF
LVPECL
(U1-9)
R3
133
C4
0.1uF
C2
0.1uF
C5
0.1uF
R1
133
R7
50
R11
50
VCCO = 3.3V
R4
82.5
(U1-25)
nQ0
VCCO = 3.3VVCC = 3.3V
(U1-24)
Q0
(U1-16)
C7
0.1uF
Zo = 50 Ohm
U1
ICS853031
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
VCC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
VEE
CLK_EN
VCCO
nQ8
Q8
nQ7
Q7
nQ6
Q6
VCCO
VCCO
nQ5
Q5
nQ4
Q4
nQ3
Q3
VCCO
VCCO
Q0
nQ0
Q1
nQ1
Q2
nQ2
VCCO
R6
50
Figure 7
shows an example of ICS853031 application schematic.
In this example, the device is operated at V
CC
= 3.3V. The
decoupling capacitor should be located as close as possible to
the power pin. The input is driven by a 3.3V LVPECL driver. Only
two terminations examples are shown in this schematic. For more
termination approaches, please refer to the LVPECL Termination
Application Note.
FIGURE 7. ICS853031 SCHEMATIC EXAMPLE
IDT
/ ICS
1-TO-9, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 15 ICS853031AY REV. C AUGUST 12, 2008
ICS853031
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853031.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853031 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V ± 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 77mA = 266.8mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 9 * 30.94mW = 278.5mW
Total Power
_MAX
(3.465V, with all outputs switching) = 266.8mW + 278.5mW = 545.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125°C.
The equation for Tj is as follows: Tj = θ
JA
* Pd_total + T
A
Tj = Junction Temperature
θ
JA
= junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.545W * 42.1°C/W = 108°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
θθ
θθ
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6. THERMAL RESISTANCE
θθ
θθ
θ
JA
FOR 32-PIN LQFP FORCED CONVECTION

ICS853031AYLF

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IC CLK BUFFER 2:9 1.6GHZ 32TQFP
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