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PL123-05NSI-R

P1-P3P4-P6P7-P8
PL123-05N/-09N
Low Skew Fanout Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/15/12 Page 4
ELECTRICAL CHARACTERISTICS (Commercial and Industrial Temperature Devices)
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
IL
Input LOW Voltage
[1]
V
DD
> 2.25V
–
0.8
V
V
IH
Input HIGH Voltage
[1]
V
DD
> 2.25V
2.0
–
V
I
IL
Input LOW Current
V
IN
= 0V
–
50
µA
I
IH
Input HIGH Current
V
IN
= V
DD
–
100
µA
V
OL
Output LOW Voltage
[2]
I
OL
= 8 mA , V
DD
> 2.97V
–
0.4
V
V
OH
Output HIGH Voltage
[2]
I
OH
= –8 mA , V
DD
> 2.97V
2.4
–
V
I
DD
Supply Current
66.67MHz with unloaded outputs
–
32
mA
SWITCHING CHARACTERISTICS (Commercial and Industrial Temperature Devices)
[3]
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
Duty Cycle
[2]
= t2 ÷ t1
Measured at 1.4V, V
DD
=3.3V, Input=50%
40
50
60
%
Measured at V
DD
/2 , Input = 50%
40
50
60
%
t
3
Rise Time
[2]
0.8V 2.0V , V
DD
=3.3V , 30pF Load
–
–
1.5
ns
10% 90% , V
DD
=2.5V , 15pF Load
–
–
2.5
ns
10% 90% , V
DD
=1.8V , 15pF Load
–
–
4.5
ns
t
4
Fall Time
[2]
2.0V 0.8V , V
DD
=3.3V , 30pF Load
–
–
1.5
ns
90% 10% , V
DD
=2.5V , 15pF Load
–
–
2.5
ns
90% 10% , V
DD
=1.8V , 15pF Load
–
–
4.5
ns
t
5
Output to Output Skew
[2]
All outputs equally loaded
–
–
250
ps
t
6
Propagation Delay, REF Rising
Edge to CLKX Rising Edge
[2]
Measured at V
DD
/2
1
5
9.2
ns
Notes:
1. REF input has a threshold voltage of V
DD
/2
2. Parameter is guaranteed by design and characterization. Not 100% tested in p roduction.
3. All parameters are specified with loaded outputs.
PL123-05N/-09N
Low Skew Fanout Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/15/12 Page 5
NOISE CHARACTERISTICS (Commercial and Industrial Temperature Devices)
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
Additive Phase Jitter
V
DD
=3.3V, Frequency=100MHz
Offset=12KHz ~ 20MHz
60
fs
PL123-09N Additive Phase Jitter:
VDD=3.3V, CLK=100MHz, Integration Range 12KHz to 20MHz: 0.059ps typical.
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
10 100 1000 10000 100000 1000000 10000000 100000000
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
REF Input PL123-09N Output
When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the
buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the
Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive
Phase Jitter is as follows:
Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter)
22
PL123-05N/-09N
Low Skew Fanout Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/15/12 Page 6
SWITCHING WAVEFORMS
TEST CIRCUIT
1.4V
1.4V
t
2
t
1
VDD/2
INPUT
t
6
OUTPUT
VDD/2
1.4V
OUTPUT
t
5
OUTPUT
1.4V
Duty Cycle Timing
All Outputs Rise/Fall Time
Output-Output Skew
Input-Output Propagation Delay
t
3
t
4
OUTPUT
0.8V
2.0V
0V
3.3V
V
0.8V
2.0V
VDD
VDD
GND
GND
OUTPUTS
C
L OAD
CLK
0.1 F
0.1 F
P1-P3P4-P6P7-P8

PL123-05NSI-R

Mfr. #:
Buy PL123-05NSI-R
Manufacturer:
Microchip Technology / Micrel
Description:
Clock Buffer DC - 134MHz 1:5 Fanout Buffer
Lifecycle:
New from this manufacturer.
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