ADDI7100 Data Sheet
Rev. D | Page 18 of 20
Address
Data
Bits
Default
Value
Update
Type
1
Name Description
0x0D [0] 0 SCK VD_POL 0: falling edge triggered
1: rising edge triggered
0x0E [6:0] 0 SCK REG_UPDATE Set the appropriate bits high to enable VD update of the selected registers:
[0]: CDSGAIN (Register 0x02)
[1]: VGAGAIN (Register 0x03)
[2]: CLAMPLEVEL (Register 0x04)
[3]: test use only; must be set to 0
[4]: test use only; must be set to 0
[5]: test use only; must be set to 0
[6]: test use only; must be set to 0
0xFF [0] 0 SCK Test Test use only; do not access
1
SCK = register is immediately updated when the 16th data bit (D15) is written. VD = register is updated at the VD falling edge.
