DS1340Z-3 Datasheet DS1340Z-3, DS1340Z-18, DS1340Z-33 | P10-P12

DS1340

Flag Register (09h)

Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit

indicates that the oscillator has stopped or was

stopped for some time period and may be used to

judge the validity of the clock and calendar data. This

bit is edge triggered and is set to logic 1 when the

internal circuitry senses that the oscillator has transi-

tioned from a normal run state to a STOP condition. The

following are examples of conditions that can cause the

OSF bit to be set:

1) The first time power is applied.

2) The voltages present on V

and V

BACKUP

are insufficient to support oscillation.

3) The EOSC bit is set to 1, disabling the

oscillator.

4) External influences on the crystal (e.g., noise,

leakage).

The OSF bit remains at logic 1 until written to logic 0. It

can only be written to logic 0. Attempting to write OSF

to logic 1 leaves the value unchanged.

Bits 6 to 0: All other bits in the flag register read as 0

and cannot be written.

Clock Calibration

The DS1340 provides a digital clock calibration feature

to allow compensation for crystal and temperature vari-

ations. The calibration circuit adds or subtracts counts

from the oscillator divider chain at the divide-by-256

stage. The number of pulses blanked (subtracted for

negative calibration) or inserted (added for positive cal-

ibration) depends upon the value loaded into the five

calibration bits (CAL4–CAL0) located in the control reg-

ister. Adding counts speeds the clock up and subtract-

ing counts slows the clock down.

The calibration bits can be set to any value between 0

and 31 in binary form. Bit 5 of the control register, S, is

the sign bit. A value of 1 for the S bit indicates positive

calibration, while a value of 0 represents negative cali-

bration. Calibration occurs within a 64-minute cycle.

The first 62 minutes in the cycle can, once per minute,

have a one-second interval where the calibration is per-

formed. Negative calibration blanks 128 cycles of the

32,768Hz oscillator, slowing the clock down. Positive

calibration inserts 256 cycles of the 32,768Hz oscillator,

speeding the clock up. If a binary 1 is loaded into the

calibration bits, only the first two minutes in the 64-

minute cycle are modified. If a binary 6 is loaded, the

first 12 minutes are affected, and so on. Therefore,

each calibration step either adds 512 or subtracts 256

oscillator cycles for every 125,829,120 actual 32,678Hz

oscillator cycles (64 minutes). This equates to

+4.068ppm or -2.034ppm of adjustment per calibration

step. If the oscillator runs at exactly 32,768Hz, each of

the 31 increments of the calibration bits would repre-

sent +10.7 or -5.35 seconds per month, corresponding

to +5.5 or -2.75 minutes per month.

For example, if using the FT function, a reading of

512.01024Hz would indicate a +20ppm oscillator fre-

quency error, requiring a -10(00 1010) value to be

loaded in the S bit and the five calibration bits.

Note: Setting the calibration bits does not affect the fre-

quency test output frequency. Also note that writing to

the control register resets the divider chain.

C RTC with Trickle Charger

10 ____________________________________________________________________

TCS3 TCS2 TCS1 TCS0 DS1 DS0

ROUT1 ROUT0

FUNCTION

X X X X 0 0 X X Disabled

X X X X 1 1 X X Disabled

XXXXXX00Disabled

1 0 1 0 0 1 0 1 No diode, 250Ω resistor

1 0 1 0 1 0 0 1 One diode, 250Ω resistor

1 0 1 0 0 1 1 0 No diode, 2kΩ resistor

1 0 1 0 1 0 1 0 One diode, 2kΩ resistor

1 0 1 0 0 1 1 1 No diode, 4kΩ resistor

1 0 1 0 1 0 1 1 One diode, 4kΩ resistor

0 0 0 0 0 0 0 0 Power-on reset value

Table 4. Trickle-Charge Register

C Serial Data Bus

The DS1340 supports a bidirectional I

C bus and data

transmission protocol. A device that sends data onto

the bus is defined as a transmitter and a device receiv-

ing data as a receiver. The device that controls the

message is called a master. The devices that are con-

trolled by the master are slaves. A master device that

generates the serial clock (SCL), controls the bus

access, and generates the START and STOP condi-

tions must control the bus. The DS1340 operates as a

slave on the I

C bus. Connections to the bus are made

through the open-drain I/O lines SDA and SCL. Within

the bus specifications a standard mode (100kHz max

clock rate) and a fast mode (400kHz max clock rate)

are defined. The DS1340 works in both modes.

The following bus protocol has been defined (Figure 7):

• Data transfer can be initiated only when the bus is

not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high are inter-

preted as control signals.

Accordingly, the following bus conditions have been

defined:

Bus not busy: Both data and clock lines remain

high.

START data transfer: A change in the data line’s

state from high to low, while the clock line is high,

defines a START condition.

STOP data transfer: A change in the data line’s

state from low to high, while the clock line is high,

defines a STOP condition.

Data valid: The data line’s state represents valid

data when, after a START condition, the data line is

stable for the duration of the high period of the

clock signal. The data on the line must be changed

during the low period of the clock signal. There is

one clock pulse per bit of data.

Each data transfer is initiated with a START condi-

tion and terminated with a STOP condition. The

number of data bytes transferred between the

START and STOP conditions is not limited, and is

determined by the master device. The information

is transferred byte-wise and each receiver

acknowledges with a ninth bit.

Acknowledge: Each receiving device, when

addressed, is obliged to generate an acknowl-

edge after the reception of each byte. The master

device must generate an extra clock pulse that is

associated with this acknowledge bit.

A device that acknowledges must pull down the

SDA line during the acknowledge clock pulse in

such a way that the SDA line is stable low during

the high period of the acknowledge-related clock

pulse. Setup and hold times must be taken into

account. A master must signal an end of data to

the slave by not generating an acknowledge bit on

the last byte that has been clocked out of the

slave. In this case, the slave must leave the data

line high to enable the master to generate the

STOP condition.

DS1340

C RTC with Trickle Charger

____________________________________________________________________ 11

STOP

CONDITION

OR REPEATED

START

CONDITION

REPEATED IF MORE BYTES

ARE TRANSFERED

ACK

START

CONDITION

ACK

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

SLAVE ADDRESS

MSB

SCL

SDA

R/W

DIRECTION

BIT

12 678 9 12 893–7

Figure 7. I

C Data Transfer Overview

DS1340

C RTC with Trickle Charger

12 ____________________________________________________________________

Figures 8 and 9 detail how data transfer is accom-

plished on the I

C bus. Depending upon the state of

the R/W bit, two types of data transfer are possible:

Data transfer from a master transmitter to a

slave receiver. The first byte transmitted by the

master is the slave address. Next follows a num-

ber of data bytes. The slave returns an acknowl-

edge bit after each received byte.

Data transfer from a slave transmitter to a mas-

ter receiver. The master transmits the first byte (the

slave address). The slave then returns an acknowl-

edge bit. Next follows a number of data bytes trans-

mitted by the slave to the master. The master

returns an acknowledge bit after all received bytes

other than the last byte. At the end of the last

received byte, a not acknowledge is returned.

The master device generates all the serial clock

pulses and the START and STOP conditions. A

transfer is ended with a STOP condition or with a

repeated START condition. Since a repeated

START condition is also the beginning of the next

serial transfer, the bus is not released.

The DS1340 can operate in the following two modes:

Slave Receiver Mode (Write Mode): Serial data

and clock are received through SDA and SCL.

After each byte is received, an acknowledge bit is

transmitted. Start and STOP conditions are recog-

nized as the beginning and end of a serial trans-

fer. Hardware performs address recognition after

reception of the slave address and direction bit.

The slave address byte is the first byte received

after the master generates the START condition.

The slave address byte contains the 7-bit DS1340

address, which is 1101000, followed by the direc-

tion bit (R/W), which is 0 for a write. After receiving

and decoding the slave address byte, the DS1340

outputs an acknowledge on SDA. After the

DS1340 acknowledges the slave address + write

bit, the master transmits a word address to the

DS1340. This sets the register pointer on the

DS1340, with the DS1340 acknowledging the

transfer. The master can then transmit zero or

more bytes of data, with the DS1340 acknowledg-

ing each byte received. The register pointer incre-

ments after each data byte is transferred. The

master generates a STOP condition to terminate

the data write.

Slave Transmitter Mode (Read Mode): The first

byte is received and handled as in the slave

receiver mode. However, in this mode, the direc-

tion bit indicates that the transfer direction is

reversed. The DS1340 transmits serial data on

SDA while the serial clock is input on SCL. Start

and STOP conditions are recognized as the begin-

ning and end of a serial transfer. Hardware per-

forms address recognition after reception of the

slave address and direction bit. The slave address

byte is the first byte received after the master gen-

erates the START condition. The slave address

byte contains the 7-bit DS1340 address, which is

1101000, followed by the direction bit (R/W),

which is 1 for a read. After receiving and decoding

the slave address byte, the DS1340 outputs an

acknowledge on SDA. The DS1340 then begins to

transmit data starting with the register address

pointed to by the register pointer. If the register

pointer is not written to before the initiation of a

read mode, the first address that is read is the last

one stored in the register pointer. The DS1340

must receive a not acknowledge to end a read.

AXXXXXXXXA1101000S 0 XXXXXXXX A XXXXXXXX A XXXXXXXX A P

<SLAVE

ADDRESS>

S — START

A — ACKNOWLEDGE

P — STOP

R/W — READ/WRITE OR DIRECTION BIT ADDRESS = D0H

<RW>

DATA TRANSFERRED

(X + 1 BYTES + ACKNOWLEDGE)

<WORD

ADDRESS (n)>

Figure 8. Slave Receiver Mode (Write Mode)

AXXXXXXXXA1101000S 1 XXXXXXXX A XXXXXXXX A XXXXXXXX A P

<SLAVE

ADDRESS>

S — START

A — ACKNOWLEDGE

P — STOP

A — NOT ACKNOWLEDGE

R/W — READ/WRITE OR DIRECTION BIT ADDRESS = D0H

<RW>

DATA TRANSFERRED

(X + 1 BYTES + ACKNOWLEDGE)

NOTE: LAST DATA BYTE IS FOLLOWED BY

A NOT ACKNOWLEDGE (A) SIGNAL

Figure 9. Slave Transmitter Mode (Read Mode

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

DS1340Z-3

Mfr. #:

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Real Time Clock I2C RTC w/Trickle Charger

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DS1340Z-3

DS1340Z-3

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