WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode.
Note 1: Limits at -40°C are guaranteed by design and not production tested.
Note 2: After this period, the first clock pulse is generated.
Note 3: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V
IH(MIN)
of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
Note 4: The maximum t
HD:DAT
only has to be met if the device does not stretch the low period (t
LOW
) of the SCL signal.
Note 5: A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
≥ to 250ns must be met. This
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line t
R MAX
+ t
SU:DAT
= 1000 + 250 = 1250ns
before the SCL line is released.
Note 6: C
B
—total capacitance of one bus line in pF.
Note 7: The parameter t
OSF
is the period of time the oscillator must be stopped for the OSF flag to be set over the 0V ≤ V
CC
≤
V
CCMAX
and 1.3V ≤ V
BAT
≤ 3.7V range.
Note 8: All voltages are referenced to ground.
Note 9: Measured at V
CC
= typ, V
BACKUP
= 0V, register 08h = A5h.
Note 10: The use of the 250Ω trickle-charge resistor is not allowed at V
CC
> 3.63V and should not be enabled.
Note 11: Measured at V
CC
= typ, V
BACKUP
= 0V, register 08h = A6h.
Note 12: Measured at V
CC
= typ, V
BACKUP
= 0V, register 08h = A7h.
Note 13: I
CCA
—SCL clocking at max frequency = 400kHz.
Note 14: Specified with I
2
C bus inactive.
Note 15: Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
Note 16: Limits at +25°C are guaranteed by design and not production tested.
Note 17: This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay
occurs.