8
Detailed Description
Theory of Operation
The HI5805 is a 12-bit, fully-differential, sampling pipeline A/D
converter with digital error correction. Figure 14 depicts the
circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
clock which is a non-overlapping two phase signal, f
1
and f
2
,
derived from the master clock. During the sampling phase, f
1
,
the input signal is applied to the sampling capacitors, C
S
. At
the same time the holding capacitors, C
H
, are discharged to
analog ground. At the falling edge of f
1
the input signal is
sampled on the bottom plates of the sampling capacitors. In
the next clock phase, f
2
, the two bottom plates of the
sampling capacitors are connected together and the holding
capacitors are switched to the op-amp output nodes. The
charge then redistributes between C
S
and C
H
completing one
sample-and-hold cycle. The output is a fully-differential,
sampled-data representation of the analog input. The circuit
not only performs the sample-and-hold function but will also
convert a single-ended input to a fully-differential output for
the converter core. During the sampling phase, the V
IN
pins
see only the on-resistance of a switch and C
S
. The relatively
small values of these components result in a typical full power
input bandwidth of 100MHz for the converter.
As illustrated in the functional block diagram and the timing
diagram in Figure 1, three identical pipeline subconverter
stages, each containing a four-bit flash converter, a four-bit
digital-to-analog converter and an amplifier with a voltage
gain of 8, follow the S/H circuit with the fourth stage being
only a 4-bit flash converter. Each converter stage in the
pipeline will be sampling in one phase and amplifying in the
other clock phase. Each individual sub-converter clock
signal is offset by 180 degrees from the previous stage
clock signal, with the result that alternate stages in the
pipeline will perform the same operation.
The 4-bit digital output of each stage is fed to a digital delay
line controlled by the internal clock. The purpose of the delay
line is to align the digital output data to the corresponding
sampled analog input signal. This delayed data is fed to the
digital error correction circuit which corrects the error in the
output data with the information contained in the redundant
bits to form the final 12-bit output for the converter.
Because of the pipeline nature of this converter, the data on
the bus is output at the 3rd cycle of the clock after the analog
sample is taken. This delay is specified as the data latency.
After the data latency time, the data representing each
succeeding sample is output at the following clock pulse. The
output data is synchronized to the external clock by a latch.
The digital outputs are in offset binary format (See Table 1).
Internal Reference Generator, V
ROUT
and V
RIN
The HI5805 has an internal reference generator, therefore, no
external reference voltage is required. V
ROUT
must be
connected to V
RIN
when using the internal reference voltage.
The HI5805 can be used with an external reference. The
converter requires only one external reference voltage
connected to the V
RIN
pin with V
ROUT
left open.
The HI5805 is tested with V
RIN
equal to 3.5V. Internal to the
converter, two reference voltages of 1.3V and 3.3V are
generated for a fully differential input signal range of 2V.
In order to minimize overall converter noise, it is
recommended that adequate high frequency decoupling be
provided at the reference voltage input pin, V
RIN
.
Pin Descriptions
PIN NO. NAME DESCRIPTION
1 CLK Input Clock.
2DV
CC1
Digital Supply (5.0V).
3D
GND1
Digital Ground.
4DV
CC1
Digital Supply (5.0V).
5D
GND1
Digital Ground
6AV
CC
Analog Supply (5.0V).
7A
GND
Analog Ground.
8V
IN
+ Positive Analog Input.
9V
IN
- Negative Analog Input.
10 V
DC
DC Bias Voltage Output.
11 V
ROUT
Reference Voltage Output.
12 V
RIN
Reference Voltage Input.
13 A
GND
Analog Ground.
14 AV
CC
Analog Supply (5.0V).
15 D11 Data Bit 11 Output (MSB).
16 D10 Data Bit 10 Output.
17 D9 Data Bit 9 Output.
18 D8 Data Bit 8 Output.
19 D7 Data Bit 7 Output.
20 D6 Data Bit 6 Output.
21 D
GND2
Digital Output Ground.
22 DV
CC2
Digital Output Supply (3.0V to 5.0V).
23 D5 Data Bit 5 Output.
24 D4 Data Bit 4 Output.
25 D3 Data Bit 3 Output.
26 D2 Data Bit 2 Output.
27 D1 Data Bit 1 Output.
28 D0 Data Bit 0 Output (LSB).
C
H
C
S
C
S
V
IN
+
V
OUT
+
V
OUT
-
V
IN
-
1
1
2
1
1
C
H
1
1
FIGURE 14. ANALOG INPUT SAMPLE-AND-HOLD
+ -
- +
HI5805
