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MT5VDDT3272HG-335F2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
PDF: 09005aef80a8e793/Source: 09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.
dd5c16_32x72h.fm - Rev. F 2/07 EN
10 ©2004 Micron Technology, Inc. All rights reserved.
128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM
Electrical Specifications
Table 10: DDR IDD Specifications and Conditions – 256MB
Values shown for MT46V32M16 DDR SDRAM only and are computed from values specified in the
512Mb (32 Meg x 16) component data sheet
Parameter/Condition Symbol -40B -335 Units
Operating one bank active-precharge current:
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
IDD0 775 650 mA
Operating one bank active-read-precharge current: Burst = 4;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); IOUT = 0mA; Address and control inputs changing
once per clock cycle
IDD1 925 800 mA
Precharge power-down standby current: All device banks idle; Power-down
mode;
t
CK =
t
CK (MIN); CKE = (LOW)
IDD2P 25 25 mA
Idle standby current: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN); CKE =
HIGH; Address and other control inputs changing once per clock cycle; V
IN = VREF for
DQ, DQS, and DM
IDD2F 275 225 mA
Active power-down standby current: One device bank active; Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD3P 225 175 mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank; Active-
precharge;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle; Address and other control inputs changing once per clock cycle
IDD3N 300 250 mA
Operating current: Burst = 2; Reads; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); IOUT = 0mA
IDD4R 950 825 mA
Operating current: Burst = 2; Writes; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
IDD4W 975 775 mA
Auto refresh current
t
REFC =
t
RFC (MIN)
IDD5 1,725 1,450 mA
t
REFC = 7.8125µs
IDD5A 55 50 mA
Self refresh current: CKE ≤ 0.2V
IDD62525mA
Operating current: Four device bank interleaving READs (BL = 4) with auto
precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address and control inputs change only
during active READ or WRITE commands
IDD7 2,250 2,025 mA
PDF: 09005aef80a8e793/Source: 09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.
dd5c16_32x72h.fm - Rev. F 2/07 EN
11 ©2004 Micron Technology, Inc. All rights reserved.
128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM
Serial Presence-Detect
Serial Presence-Detect
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
Table 11: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
Parameter/Condition Symbol Min Max Units
Supply voltage
V
DDSPD 2.3 3.6 V
Input high voltage: Logic 1; All inputs
V
IH VDDSPD × 0.7 VDDSPD + 0.5 V
Input low voltage: Logic 0; All inputs
V
IL –1 VDDSPD × 0.3 V
Output low voltage: I
OUT = 3mA
V
OL –0.4V
Input leakage current: V
IN = GND to VDD
ILI –10µA
Output leakage current: V
OUT = GND to VDD
ILO –10µA
Standby current: SCL = SDA = V
DD - 0.3V; All other inputs = VSS or VDD
ISB –30µA
Power supply current: SCL clock frequency = 100 kHz
I
CC –2mA
Table 12: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time the bus must be free before a new transition can start
t
BUF 1.3 – µs
Data-out hold time
t
DH 200 – ns
SDA and SCL fall time
t
F–300ns2
Data-in hold time
t
HD:DAT 0 – µs
Start condition hold time
t
HD:STA 0.6 – µs
Clock HIGH period
t
HIGH 0.6 – µs
Noise suppression time constant at SCL, SDA inputs
t
I–50ns
Clock LOW period
t
LOW 1.3 – µs
SDA and SCL rise time
t
R–0.3µs2
SCL clock frequency
f
SCL – 400 kHz
Data-in setup time
t
SU:DAT 100 – ns
Start condition setup time
t
SU:STA 0.6 – µs 3
Stop condition setup time
t
SU:STO 0.6 – µs
WRITE cycle time
t
WRC – 10 ms 4
PDF: 09005aef80a8e793/Source: 09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.
dd5c16_32x72h.fm - Rev. F 2/07 EN
12 ©2004 Micron Technology, Inc. All rights reserved.
128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM
Serial Presence-Detect
Table 13: Serial Presence-Detect Matrix (-335, -26A, and -265 Speed Grades)
Byte Description Entry (Version) 128MB 256MB
0
Number of SPD bytes used by Micron
128 80 80
1
Total number of bytes in SPD device
256 08 08
2
Fundamental memory type
DDR SDRAM 07 07
3
Number of row addresses on assembly
12,13 0D 0D
4
Number of column addresses on assembly
9, 10 09 0A
5
Number of physical ranks on DIMM
10101
6
Module data width
72 48 48
7
Module data width (continued)
00000
8
Module voltage interface levels
SSTL 2.5V 04 04
9
SDRAM cycle time,
t
CK, CL = 2.5
6ns (-335)
7ns (-262/-26A)
7.5ns (-265)
60
70
75
60
70
75
10
SDRAM access from clock,
t
AC, CL = 2.5
0.7ns (-335)
0.75ns (-262/-26A/
-265)
70
75
70
75
11
Module configuration type
ECC 02 02
12
Refresh rate/type
15.62µs, 7.8µs/SELF 82 82
13
SDRAM device width (primary DDR SDRAM)
16 10 10
14
Error-checking DDR SDRAM data width
16 10 10
15
MIN clock delay, back-to-back random column
access
1 clock 01 01
16
Burst lengths supported
2, 4, 8 0E 0E
17
Number of banks on DDR SDRAM device
40404
18
CAS latencies supported
2.5, 2 0C 0C
19
CS latency
00101
20
WE latency
10202
21
SDRAM module attributes
Unbuffered/diff. clock 20 20
22
SDRAM device attributes: general
Fast/concurrent AP C1 C1
23
SDRAM cycle time,
t
CK, CL = 2
7.5ns (-335/-262/-26A)
10ns (-265)
75
A0
75
A0
24
SDRAM access from clock,
t
AC, CL = 2
0.7ns (-335)
0.75ns (-262/-26A/
-265)
70
75
70
75
25
SDRAM cycle time,
t
CK, CL = 1.5
00 00
26
SDRAM access from CK,
t
AC, CL = 1.5
00 00
27
MIN row precharge time,
t
RP
4
18ns (-335)
15ns (-262)
20ns (-26A/-265)
48
3C
50
48
3C
50
28
MIN row active-to-row active,
t
RRD
12ns (-335)
15ns (-262/-26A/-265)
30
3C
30
3C
29
MIN RAS#-to-CAS# delay,
t
RCD
4
18ns (-335)
15ns (-262)
20ns (-26A/-265)
48
3C
50
48
3C
50
30
MIN RAS# pulse width,
t
RAS
2
42ns (-335)
45ns (-262/-26A/-265)
2A
2D
2A
2D
31
Module rank density
128MB, 256MB 20 40
32
Address and command setup time,
t
IS
3
0.8ns (-335)
1.0ns (-262/-26A/-265)
80
A0
80
A0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

MT5VDDT3272HG-335F2

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Buy MT5VDDT3272HG-335F2
Manufacturer:
Micron
Description:
MODULE DDR SDRAM 256MB 200SODIMM
Lifecycle:
New from this manufacturer.
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