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CY7C1021BNL-15ZXC

P1-P3P4-P6P7-P9P10-P10
CY7C1021BN
CY7C10211BN
Document #: 001-06494 Rev. *A Page 4 of 10
Thermal Resistance
[4]
Parameter Description Test Conditions 44-pin SOJ 44-pin TSOP-II Unit
Θ
JA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA / JESD51.
64.32 76.89 °C/W
Θ
JC
Thermal Resistance
(Junction to Case)
31.03 14.28 °C/W
AC Test Loads and Waveforms
Switching Characteristics
[5]
Over the Operating Range
Parameter Description
7C10211B-10 7C1021B-12 7C1021B-15
UnitMin. Max. Min. Max. Min. Max.
Read Cycle
t
RC
Read Cycle Time 10 12 15 ns
t
AA
Address to Data Valid 10 12 15 ns
t
OHA
Data Hold from Address Change 3 3 3 ns
t
ACE
CE LOW to Data Valid 10 12 15 ns
t
DOE
OE LOW to Data Valid 5 6 7 ns
t
LZOE
OE LOW to Low Z
[6]
000ns
t
HZOE
OE HIGH to High Z
[6, 7]
567ns
t
LZCE
CE LOW to Low Z
[6]
333ns
t
HZCE
CE HIGH to High Z
[6, 7]
567ns
t
PU
CE LOW to Power-Up 0 0 0 ns
t
PD
CE HIGH to Power-Down 10 12 15 ns
t
DBE
Byte Enable to Data Valid 5 6 7 ns
t
LZBE
Byte Enable to Low Z 0 0 0 ns
t
HZBE
Byte Disable to High Z 5 6 7 ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state
voltage.
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R 481Ω
R 481Ω
R2
255
R2
255
167
Equivalent to:
THÉVENIN
EQUIVALENT
1.73V
30 pF
Rise Time: 1 V/ns Fall Time: 1 V/ns
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R2
255Ω
R2
255Ω
167
Equivalent to:
THÉVENIN
EQUIVALENT
30 pF
Rise Time: 1 V/ns
[+] Feedback
CY7C1021BN
CY7C10211BN
Document #: 001-06494 Rev. *A Page 5 of 10
Write Cycle
[8]
t
WC
Write Cycle Time 10 12 15 ns
t
SCE
CE LOW to Write End 8 9 10 ns
t
AW
Address Set-Up to Write End 7 8 10 ns
t
HA
Address Hold from Write End 0 0 0 ns
t
SA
Address Set-Up to Write Start 0 0 0 ns
t
SD
Data Set-Up to Write End 5 6 8 ns
t
HD
Data Hold from Write End 0 0 0 ns
t
LZWE
WE HIGH to Low Z
[6]
333ns
t
HZWE
WE LOW to High Z
[6, 7]
567ns
t
BW
Byte Enable to End of Write 7 8 9 ns
Switching Waveforms
Read Cycle No. 1
[9, 10]
Read Cycle No. 2 (OE Controlled)
[10, 11]
Notes:
8. The internal write time of the memory is defined by the overlap of CE
LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a
write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that
terminates the write.
9. Device is continuously selected. OE
, CE, BHE and/or BHE = V
IL
.
10.WE
is HIGH for read cycle.
Switching Characteristics
[5]
Over the Operating Range (continued)
Parameter Description
7C10211B-10 7C1021B-12 7C1021B-15
UnitMin. Max. Min. Max. Min. Max.
PREVIOUS DATA VALID DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZBE
t
PD
HIGH
ICC
ISB
IMPEDANCE
DATA
t
DBE
t
LZBE
t
HZCE
I
CC
I
SB
ADDRESS
OE
CE
BHE,BLE
OUT
V
CC
SUPPLY
CURRENT
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CY7C1021BN
CY7C10211BN
Document #: 001-06494 Rev. *A Page 6 of 10
Write Cycle No. 1 (CE Controlled)
[12, 13]
Write Cycle No. 2 (BLE or BHE Controlled)
Notes:
11. Address valid prior to or coincident with CE
transition LOW.
12.Data I/O is high impedance if OE
or BHE and/or BLE= V
IH
.
13.If CE
goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Switching Waveforms (continued)
t
HD
t
SD
t
SCE
t
SA
t
HA
t
AW
t
PWE
t
WC
BW
DATA
ADDRESS
BHE
,
t
CE
ADDRESS
WE
BLE
I/O
t
HD
t
SD
t
BW
t
SA
t
HA
t
AW
t
PWE
t
WC
t
SCE
DATA I/O
ADDRESS
BHE
,BLE
WE
CE
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CY7C1021BNL-15ZXC

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Buy CY7C1021BNL-15ZXC
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 1M PARALLEL 44TSOP II
Lifecycle:
New from this manufacturer.
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