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LTC5543IUH#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
LTC5543
10
5543f
Introduction
The LTC5543 consists of a high linearity passive double-
balanced mixer core, IF buffer amplifi er, high speed single-
pole double-throw (SPDT) LO switch, LO buffer amplifi er
and bias/shutdown circuits. See Block Diagram section for
a description of each pin function. The RF and LO inputs
are single-ended. The IF output is differential. Low-side or
high-side LO injection can be used. The evaluation circuit,
shown in Figure 1, utilizes bandpass IF output matching and
an IF transformer to realize a 50 single-ended IF output.
The evaluation board layout is shown in Figure 2.
APPLICATIONS INFORMATION
Figure 2. Evaluation Board Layout
RF Input
The mixer’s RF input, shown in Figure 3, is connected to
the primary winding of an integrated transformer. A 50
match is realized with a series inductor (L4) and a shunt
capacitor (C11). The primary side of the RF transformer
is DC-grounded internally and the DC resistance of the
primary is approximately 3.2. A DC blocking capacitor
is needed if the RF source has DC voltage present.
The secondary winding of the RF transformer is internally
connected to the passive mixer. The center-tap of the
transformer secondary is connected to pin 3 (CT) to allow
the connection of bypass capacitor, C2. The value of C2
is LO frequency-dependent and is not required for most
5543 F02
applications. When used, C2 should be located within
2mm of pin 3 for proper high-frequency decoupling. The
nominal DC voltage on the CT pin is 1.2V.
For the RF input to be matched, the selected LO input
must be driven. A broadband input match is realized with
L4 = 1.2nH and C11 = 0.8pF. The measured RF input return
loss is shown in Figure 4 for LO frequencies of 2.6GHz,
3.0GHz and 3.4GHz. These LO frequencies correspond to
the lower, middle and upper values of the LO range. As
shown in Figure 4, the RF input impedance is somewhat
dependent on LO frequency.
LTC5543
C2
RF
IN
CT
RF
TO MIXER
2
3
5543 F03
C11
L4
Figure 3. RF Input Schematic
Figure 4. RF Input Return Loss
FREQUENCY (GHz)
2
35
RF PORT RETURN LOSS (dB)
5
15
10
20
25
30
0
42.2 2.4 2.6 2.8 3 3.2 3.4
5543 F04
3.6 3.8
LO = 3.4GHz
LO = 3.0GHz
LO = 2.6GHz
LTC5543
11
5543f
APPLICATIONS INFORMATION
The RF input impedance and input refl ection coeffi cient,
versus RF frequency, is listed in Table 1. The reference
plane for this data is pin 2 of the IC, with no external
matching, and the LO is driven at 2.69GHz.
Table 1. RF Input Impedance and S11
(at Pin 2, No External Matching, LO Input Driven at 2.69GHz)
FREQUENCY
(GHz)
INPUT
IMPEDANCE
S11
MAG ANGLE
2.0 44.6 + j14.7 0.16 101.3
2.2 41.0 + j11.9 0.16 119.7
2.4 37.7 + j10.7 0.18 132.0
2.6 31.7 + j9.4 0.25 146.2
2.8 26.2 + j18.8 0.38 127.8
3.0 28.3 + j22.4 0.38 118.1
3.2 28.2 + j24.5 0.40 114.3
3.4 27.7 + j27.8 0.43 109.0
3.6 28.7 + j31.2 0.46 102.7
3.8 29.9 + j32.8 0.45 99.2
4.0 30.4 + j33.4 0.44 97.8
LO2
IN
LO1
IN
V
CC2
V
CC1
V
CC3
LO BUFFER
TO
MIXER
LTC5543
LO1
LOSELLOBIAS
LO2
5543 F05
15
11
9
8
6
BIAS
7
C4
C3
4mA
14
LO Inputs
The mixer’s LO input circuit, shown in Figure 5, consists
of an integrated SPDT switch, a balun transformer, and
a two-stage high-speed limiting differential amplifi er to
drive the mixer core. The LTC5543’s LO amplifi ers are
optimized for the 2.4GHz to 3.6GHz LO frequency range.
LO frequencies above or below this frequency range may
be used with degraded performance.
Figure 5. LO Input Schematic
The LO switch is designed for high isolation and fast
(<50ns) switching. This allows the use of two active
synthesizers in frequency-hopping applications. If only
one synthesizer is used, then the unused LO input may
be grounded. The LO switch is powered by V
CC3
(Pin 14)
and controlled by the LOSEL logic input (Pin 9). The LO1
and LO2 inputs are always 50-matched when V
CC
is
applied to the chip, even when the chip is shutdown. The
DC resistance of the selected LO input is approximately
20 and the unselected input is approximately 50. A
logic table for the LO switch is shown in Table 2. Measured
LO input return loss is shown in Figure 6.
Table 2. LO Switch Logic Table
LOSEL ACTIVE LO INPUT
Low LO1
High LO2
The LO amplifi ers are powered by V
CC1
and V
CC2
(pin 8
and pin 6). When the chip is enabled (SHDN = low), the
internal bias circuit provides a regulated 4mA current to the
amplifi er’s bias input, which in turn causes the amplifi ers
to draw approximately 90mA of DC current. This 4mA
reference current is also connected to LOBIAS (Pin 7)
to allow modifi cation of the amplifi er’s DC bias current
for special applications. The recommended application
circuits require no LO amplifi er bias modifi cation, so this
pin should be left open-circuited.
Figure 6. LO Input Return loss
LO FREQUENCY (GHz)
2.2
22
RETURN LOSS (dB)
4
8
6
2
12
10
14
20
18
16
0
3.82.4 2.6 32.8
5543 F06
3.2 3.4 3.6
NOT SELECTED
OR SHUTDOWN
SELECTED
LTC5543
12
5543f
APPLICATIONS INFORMATION
The nominal LO input level is 0dBm although the limiting
amplifi ers will deliver excellent performance over a ±6dB
input power range. LO input power greater than 6dBm
may cause conduction of the internal ESD diodes. Series
capacitors C3 and C4 optimize the input match and provide
DC blocking.
The LO1 input impedance and input refl ection coeffi cient,
versus frequency, is shown in Table 3. The LO2 port
is identical due to the symmetric device layout and
packaging.
Table 3. LO1 Input Impedance vs Frequency
(at Pin 11, No External Matching, LOSEL = Low)
FREQUENCY
(GHz)
INPUT
IMPEDANCE
S11
MAG ANGLE
2.0 28.9 + j3.6 0.27 167.7
2.2 30.8 + j8.7 0.26 149.5
2.4 33.4 + j11.7 0.24 136.8
2.6 34.6 + j13.7 0.24 129.1
2.8 35.3 + j16.2 0.25 121.5
3.0 36.0 + j18.8 0.27 114.3
3.2 37.2 + j22.1 0.28 105.9
3.4 38.7 + j24.6 0.30 99.2
3.6 39.4 + j26.9 0.31 94.8
3.8 39.7 + j29.1 0.33 91.5
4.0 39.6 + j32.4 0.36 87.9
IF Output
The IF amplifi er, shown in Figure 7, has differential open-
collector outputs (IF
+
and IF
–
), a DC ground return pin
(IFGND), and a pin for modifying the internal bias (IFBIAS).
The IF outputs must be biased at the supply voltage (V
CCIF
),
which is applied through matching inductors L1 and L2.
Alternatively, the IF outputs can be biased through the
center tap of a transformer. The common node of L1 and
L2 can be connected to the center tap of the transformer.
Each IF output pin draws approximately 51mA of DC
supply current (102mA total). IFGND (pin 16) must
be grounded or the amplifi er will not draw DC current.
Grounding through inductor L3 may improve LO-IF and
RF-IF leakage performance in some applications, but is
otherwise not necessary. High DC resistance in L3 will
reduce the IF amplifi er supply current, which will degrade
RF performance.
4:1
T1
IF
OUT
V
CC
C10
L2L1
C8
L3 (OR SHORT)
V
CCIF
16181920
IF
AMP
BIAS
102mA
4mA
IFGND
LTC5543
IFBIAS IF
–
IF
+
R1
(OPTION TO
REDUCE
DC POWER)
5543 F07
Figure 7. IF Amplifi er Schematic with Transformer-Based
Bandpass Match
For optimum single-ended performance, the differential
IF outputs must be combined through an external IF
transformer or discrete IF balun circuit. The evaluation
board (see Figures 1 and 2) uses a 4:1 ratio IF transformer
for impedance transformation and differential to single-
ended transformation. It is also possible to eliminate the
IF transformer and drive differential fi lters or amplifi ers
directly.
The IF output impedance can be modeled as 320 in
parallel with 2.4pF at IF frequencies. An equivalent small-
signal model (including bondwire inductance) is shown in
Figure 8. Frequency-dependent differential IF output
impedance is listed in Table 4. This data is referenced
to the package pins (with no external components) and
includes the effects of IC and package parasitics.
19
18
IF
+
IF
–
0.9nH0.9nH
R
IF
C
IF
LTC5543
5543 F08
Figure 8. IF Output Small-Signal Model
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

LTC5543IUH#PBF

Mfr. #:
Buy LTC5543IUH#PBF
Manufacturer:
Analog Devices Inc.
Description:
RF Mixer 2.3GHz - 4.0GHz High Dynamic Range Downconverting Mixer
Lifecycle:
New from this manufacturer.
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