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Product data sheet Rev. 5 — 19 February 2014 16 of 33
NXP Semiconductors
NVT2003/04/06
Bidirectional voltage-level translator
12. Performance curves
t
PLH
up-translation is typically dominated by the RC time constant, i.e.,
C
L(tot)
R
PU
=50pF 197 = 9.85 ns, but the R
on
C
L(tot)
=50pF 5 =0.250ns.
t
PHL
is typically dominated by the external pull-down driver + R
on
, which is typically small
compared to the t
PLH
in an up-translation case.
Enable/disable times are dominated by the RC time constant on the EN pin since the
transistor turn off is on the order of ns, but the enable RC is on the order of ms.
Fall time is dominated by the external pull-down driver with only a slight R
on
addition.
Rise time is dominated by the R
PU
C
L
.
Skew time within the part is virtually non-existent, dominated by the difference in bond
wire lengths, which is typically small compared to the board-level routing differences.
Maximum data rate is dominated by the system capacitance and pull-up resistors.
(1) V
I(EN)
= 1.5 V; I
O
=64mA; V
I
=0V.
(2) V
I(EN)
= 4.5 V; I
O
=15mA; V
I
=2.4V.
(3) V
I(EN)
= 2.3 V; I
O
=64mA; V
I
=0V.
(4) V
I(EN)
= 3.0 V; I
O
=64mA; V
I
=0V.
(5) V
I(EN)
= 4.5 V; I
O
=64mA; V
I
=0V.
(1) V
I(EN)
= 3.0 V; I
O
=15mA; V
I
=2.4V.
(2) V
I(EN)
= 2.3 V; I
O
=15mA; V
I
=1.7V.
Fig 16. NVT2006 typical capacitance versus propagation delay
0.2
0.4
0.6
t
PD
(ns)
0
C (pF)
0 1008040 6020
002aaf707
(1)
(2)
(3)
(4)
(5)
1
2
3
t
PD
(ns)
0
C (pF)
0 1008040 6020
002aaf708
(1)
(2)
