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74HC573N,652

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 4 of 21
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration DIP20, SO20, SSOP20 and
TSSOP20
Fig 6. Pin configuration DHVQFN20
DDH











2( 9
&&
' 4
' 4
' 4
' 4
' 4
' 4
' 4
' 4
*1' /(
+&
+&7
DDH
+&
+&7
7UDQVSDUHQWWRSYLHZ
4
'
'
4
' 4
' 4
' 4
' 4
' 4
'
*1'

4
*1'
/(
2(
9
&&











WHUPLQDO
LQGH[DUHD
Table 2. Pin description
Symbol Pin Description
OE
1 3-state output enable input (active LOW)
D[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input
GND 10 ground (0 V)
LE 11 latch enable input (active HIGH)
Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state latch output
V
CC
20 supply voltage
74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 5 of 21
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
6. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
7. Limiting values
[1] For DIP20 package: P
tot
derates linearly with 12 mW/K above 70 C.
[2] For SO20: P
tot
derates linearly with 8 mW/K above 70 C.
For SSOP20 and TSSOP20 packages: P
tot
derates linearly with 5.5 mW/K above 60 C.
For DHVQFN20 package: P
tot
derates linearly with 4.5 mW/K above 60 C.
Table 3. Function table
[1]
Operating mode Control Input Internal
latches
Output
OE LE Dn Qn
Enable and read register (transparent
mode)
LHLLL
HHH
Latch and read register L L l L L
hHH
Latch register and disable outputs H L l L Z
hHZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
CC
+0.5 V - 20 mA
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
CC
+0.5V - 20 mA
I
O
output current V
O
= 0.5 V to (V
CC
+0.5V) - 35 mA
I
CC
supply current - +70 mA
I
GND
ground current - 70 mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation DIP20 package
[1]
- 750 mW
SO20, SSOP20, TSSOP20 and
DHVQFN20 packages
[2]
- 500 mW
74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 6 of 21
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC573 74HCT573 Unit
Min Typ Max Min Typ Max
V
CC
supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
V
I
input voltage 0 - V
CC
0-V
CC
V
V
O
output voltage 0 - V
CC
0-V
CC
V
T
amb
ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate V
CC
= 2.0 V - - 625 - - - ns/V
V
CC
= 4.5 V - 1.67 139 - 1.67 139 ns/V
V
CC
= 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC573
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
V
CC
= 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
V
CC
= 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
V
CC
= 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
V
CC
= 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
V
OH
HIGH-level
output voltage
V
I
=V
IH
or V
IL
I
O
= 20 A; V
CC
= 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
I
O
= 20 A; V
CC
= 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
I
O
= 20 A; V
CC
= 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
I
O
= 6.0 mA; V
CC
= 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
I
O
= 7.8 mA; V
CC
= 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
V
OL
LOW-level
output voltage
V
I
=V
IH
or V
IL
I
O
=20A; V
CC
= 2.0 V - 0 0.1 - 0.1 - 0.1 V
I
O
=20A; V
CC
= 4.5 V - 0 0.1 - 0.1 - 0.1 V
I
O
=20A; V
CC
= 6.0 V - 0 0.1 - 0.1 - 0.1 V
I
O
= 6.0 mA; V
CC
= 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
I
O
= 7.8 mA; V
CC
= 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
I
I
input leakage
current
V
I
=V
CC
or GND;
V
CC
=6.0V
--0.1 - 1.0 - 1.0 A
I
OZ
OFF-state
output current
V
I
=V
IH
or V
IL
;
V
O
=V
CC
or GND;
V
CC
=6.0V
--0.5 - 5.0 - 10.0 A
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

74HC573N,652

Mfr. #:
Buy 74HC573N,652
Manufacturer:
NXP Semiconductors
Description:
IC LATCH OCTAL D 3STATE 20DIP
Lifecycle:
New from this manufacturer.
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