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74HC573N,652

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 7 of 21
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
I
CC
supply current V
I
=V
CC
or GND; I
O
=0A;
V
CC
=6.0V
- - 8.0 - 80 - 160 A
C
I
input
capacitance
-3.5- pF
74HCT573
V
IH
HIGH-level
input voltage
V
CC
= 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
V
IL
LOW-level
input voltage
V
CC
= 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
V
OH
HIGH-level
output voltage
V
I
=V
IH
or V
IL
; V
CC
=4.5V
I
O
= 20 A 4.4 4.5 - 4.4 - 4.4 - V
I
O
= 6 mA 3.98 4.32 - 3.84 - 3.7 - V
V
OL
LOW-level
output voltage
V
I
=V
IH
or V
IL
; V
CC
=4.5V
I
O
=20A - 0 0.1 - 0.1 - 0.1 V
I
O
= 6.0 mA - 0.16 0.26 - 0.33 - 0.4 V
I
I
input leakage
current
V
I
=V
CC
or GND;
V
CC
=5.5V
--0.1 - 1.0 - 1.0 A
I
OZ
OFF-state
output current
V
I
=V
IH
or V
IL
; V
CC
=5.5V;
V
O
=V
CC
or GND per input
pin; other inputs at V
CC
or
GND; I
O
=0A
--0.5 - 5.0 - 10 A
I
CC
supply current V
I
=V
CC
or GND; I
O
=0A;
V
CC
=5.5V
- - 8.0 - 80 - 160 A
I
CC
additional
supply current
V
I
=V
CC
2.1 V;
other inputs at V
CC
or GND;
V
CC
= 4.5 V to 5.5 V;
I
O
=0A
per input pin; Dn inputs - 35 126 - 158 - 172 A
per input pin; LE input - 65 234 - 293 - 319 A
per input pin; OE
input - 125 450 - 563 - 613 A
C
I
input
capacitance
-3.5- - - - -pF
Table 6. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 8 of 21
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC573
t
pd
propagation
delay
Dn to Qn; see Figure 7
[1]
V
CC
= 2.0 V - 47 150 - 190 - 225 ns
V
CC
= 4.5 V - 17 30 - 38 - 45 ns
V
CC
=5V; C
L
=15pF - 14 - - - - - ns
V
CC
= 6.0 V - 14 26 - 33 - 38 ns
t
pd
propagation
delay
LE to Qn; see Figure 8
[1]
V
CC
= 2.0 V - 50 150 - 190 - 225 ns
V
CC
= 4.5 V - 18 30 - 38 - 45 ns
V
CC
=5V; C
L
=15pF - 15 - - - - - ns
V
CC
= 6.0 V - 14 26 - 33 - 38 ns
t
en
enable time OE to Qn; see Figure 9
[2]
V
CC
= 2.0 V - 44 140 - 175 - 210 ns
V
CC
= 4.5 V - 16 28 - 35 - 42 ns
V
CC
= 6.0 V - 13 24 - 30 - 36 ns
t
dis
disable time OE to Qn; see Figure 9
[3]
V
CC
= 2.0 V - 55 150 - 190 - 225 ns
V
CC
= 4.5 V - 20 30 - 38 - 45 ns
V
CC
= 6.0 V - 16 26 - 33 - 38 ns
t
t
transition
time
Qn; see Figure 7
[4]
V
CC
= 2.0 V - 14 60 - 75 - 90 ns
V
CC
= 4.5 V - 5 12 - 15 - 18 ns
V
CC
= 6.0 V - 4 10 - 13 - 15 ns
t
W
pulse width LE HIGH; see Figure 8
V
CC
= 2.0 V 80 14 - 100 - 120 - ns
V
CC
= 4.5 V 16 5 - 20 - 24 - ns
V
CC
= 6.0 V 14 4 - 17 - 20 - ns
t
su
set-up time Dn to LE; see Figure 10
V
CC
= 2.0 V 50 11 - 65 - 75 - ns
V
CC
= 4.5 V 10 4 - 13 - 15 - ns
V
CC
= 6.0 V 9 3 - 11 - 13 - ns
t
h
hold time Dn to LE; see Figure 10
V
CC
= 2.0 V 5 3 - 5 - 5 - ns
V
CC
= 4.5 V 5 1 - 5 - 5 - ns
V
CC
= 6.0 V 5 1 - 5 - 5 - ns
C
PD
power
dissipation
capacitance
C
L
=50pF;f=1 MHz;
V
I
=GNDtoV
CC
[5]
-26- - - - -pF
74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 9 of 21
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
[1] t
pd
is the same as t
PLH
and t
PHL
.
[2] t
en
is the same as t
PZH
and t
PZL
.
[3] t
dis
is the same as t
PLZ
and t
PHZ
.
[4] t
t
is the same as t
THL
and t
TLH
.
[5] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
74HCT573
t
pd
propagation
delay
Dn to Qn; see Figure 7
[1]
V
CC
= 4.5 V - 20 35 - 44 - 53 ns
V
CC
=5V; C
L
=15pF - 17 - - - - - ns
t
pd
propagation
delay
LE to Qn; see Figure 8
[1]
V
CC
= 4.5 V - 18 35 - 44 - 53 ns
V
CC
=5V; C
L
=15pF - 15 - - - - - ns
t
en
enable time OE to Qn; see Figure 9
[2]
V
CC
= 4.5 V - 17 30 - 38 - 45 ns
t
dis
disable time OE to Qn; see Figure 9
[3]
V
CC
= 4.5 V - 18 30 - 38 - 45 ns
t
t
transition
time
Qn; see Figure 7
[4]
V
CC
= 4.5 V - 5 12 - 15 - 18 ns
t
W
pulse width LE HIGH; see Figure 8
V
CC
= 4.5 V 16 5 - 20 - 24 - ns
t
su
set-up time Dn to LE; see Figure 10
V
CC
= 4.5 V 13 7 - 16 - 20 - ns
t
h
hold time Dn to LE; see Figure 10
V
CC
= 4.5 V 9 4 - 11 - 15 - ns
C
PD
power
dissipation
capacitance
C
L
=50pF;f=1 MHz;
V
I
=GNDtoV
CC
1.5 V
[5]
-26- - - - -pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

74HC573N,652

Mfr. #:
Buy 74HC573N,652
Manufacturer:
NXP Semiconductors
Description:
IC LATCH OCTAL D 3STATE 20DIP
Lifecycle:
New from this manufacturer.
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