L6562ATD Datasheet L6562ATDTR, L6562ATD | P13-P15

Application information L6562AT

13/25

When the load of a PFC pre-regulator is very low, the output voltage tends to stay steadily

above the nominal value, which cannot be handled by the Dynamic OVP. If this occurs,

however, the error amplifier output will saturate low; hence, when this is detected the

external power transistor is switched off and the IC put in an idle state (static OVP). Normal

operation is resumed as the error amplifier goes back into its linear region. As a result, the

device will work in burst-mode, with a repetition rate that can be very low.

When either OVP is activated the quiescent consumption of the IC is reduced to minimize

the discharge of the Vcc capacitor and increase the hold-up capability of the IC supply

system.

7.2 Disable function

The INV pin doubles its function as a not-latched IC disable: a voltage below 0.2 V shuts

down the IC and reduces its consumption at a lower value. To restart the IC, the voltage on

the pin must exceed 0.45 V. The main usage of this function is a remote ON/OFF control

input that can be driven by a PWM controller for power management purposes. However it

also offers a certain degree of additional safety since it will cause the IC to shutdown in case

the lower resistor of the output divider is shorted to ground or if the upper resistor is missing

or fails open.

7.3 THD optimizer circuit

The device is equipped with a special circuit that reduces the conduction dead-angle

occurring to the AC input current near the zero-crossings of the line voltage (crossover

distortion). In this way the THD (total harmonic distortion) of the current is considerably

reduced.

A major cause of this distortion is the inability of the system to transfer energy effectively

when the instantaneous line voltage is very low. This effect is magnified by the high-

frequency filter capacitor placed after the bridge rectifier, which retains some residual

voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input

current flow to temporarily stop.

Application information L6562AT

14/25

Figure 19. THD optimization: standard TM PFC controller (left side) and L6562AT

(right side)

To overcome this issue the circuit embedded in the device forces the PFC pre-regulator to

process more energy near the line voltage zero-crossings as compared to that commanded

by the control loop. This will result in both minimizing the time interval where energy transfer

is lacking and fully discharging the high-frequency filter capacitor after the bridge. The effect

of the circuit is shown in figure 2, where the key waveforms of a standard TM PFC controller

are compared to those of the L6562AT.

Essentially, the circuit artificially increases the ON-time of the power switch with a positive

offset added to the output of the multiplier in the proximity of the line voltage zero-crossings.

This offset is reduced as the instantaneous line voltage increases, so that it becomes

negligible as the line voltage moves toward the top of the sinusoid.

To maximally benefit from the THD optimizer circuit, the high-frequency filter capacitor after

the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large

capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself -

even with an ideal energy transfer by the PFC pre-regulator - thus making the action of the

optimizer circuit little effective.

Imains

Vdrain

Imains

Vdrain

Input current Input current

MOSFET's drain voltage

Rectified mains voltage Rectified mains voltage

Input current

Application information L6562AT

15/25

7.4 Operating with no auxiliary winding on the boost inductor

To generate the synchronization signal on the ZCD pin, the typical approach requires the

connection between the pin and an auxiliary winding of the boost inductor through a limiting

resistor. When the device is supplied by the cascaded DC-DC converter, it is necessary to

introduce a supplementary winding to the PFC choke just to operate the ZCD pin.

Another solution could be implemented by simply connecting the ZCD pin to the drain of the

power MOSFET through an R-C network as shown in figure 3: in this way the high-

frequency edges experienced by the drain will be transferred to the ZCD pin, hence arming

and triggering the ZCD comparator.

Also in this case the resistance value must be properly chosen to limit the current

sourced/sunk by the ZCD pin. In typical applications with output voltages around 400 V,

recommended values for these components are 22 pF (or 33 pF) for C

ZCD

and 330 kΩ for

ZCD

. With these values proper operation is guaranteed even with few volts difference

between the regulated output voltage and the peak input voltage

Figure 20. ZCD pin synchronization without auxiliary winding

L6562

ZCD

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

L6562ATD

Mfr. #:

Buy L6562ATD

Manufacturer:

STMicroelectronics

Description:

Power Factor Correction - PFC Transition-mode PFC controller

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New from this manufacturer.

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L6562ATD

L6562ATD

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