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74HC08N,652
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P16
74HC_HCT08
All informatio
n provided in thi
s document is su
bject to legal
disclaimers.
© NXP B.V
. 201
2. All rights rese
rved.
Product data sheet
Rev
. 4 —
6 September 2012
7 of 16
NXP Semiconductors
74HC08; 74HCT08
Quad 2-input AND gate
T
est data is given in
T
able 9
.
Definitions test circuit:
R
T
= termination resistance should be equal to output impedance Z
o
of the pulse generator
.
C
L
= load capacitance including jig and probe capacitance.
Fig 7.
Load circuitry
for measuring swit
ching times
001aah768
t
W
t
W
t
r
t
r
t
f
V
M
V
I
negative
pulse
GND
V
I
positive
pulse
GND
10 %
90 %
90 %
10 %
V
M
V
M
V
M
t
f
V
CC
DUT
R
T
V
I
V
O
C
L
G
T
able 9.
T
est data
Ty
p
e
Input
Load
Te
s
t
V
I
t
r
, t
f
C
L
74HC08
V
CC
6.0 ns
15 pF
, 50
pF
t
PLH
, t
PHL
74HCT08
3.0 V
6.0 n
s
15 pF
, 50
pF
t
PLH
, t
PHL
74HC_HCT08
All informatio
n provided in thi
s document is su
bject to legal
disclaimers.
© NXP B.V
. 201
2. All rights rese
rved.
Product data sheet
Rev
. 4 —
6 September 2012
8 of 16
NXP Semiconductors
74HC08; 74HCT08
Quad 2-input AND gate
12. Package
outline
Fig 8.
Package outline
SOT27-1 (DIP14)
UNIT
A
max.
1
2
(1)
(1)
b
1
cD
(1)
Z
Ee
M
H
L
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT27-1
99-12-27
03-02-13
A
min.
A
max.
b
max.
w
M
E
e
1
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
0.254
2.54
7.62
8.25
7.80
10.0
8.3
2.2
4.2
0.51
3.2
0.068
0.044
0.021
0.015
0.77
0.73
0.014
0.009
0.26
0.24
0.14
0.12
0.01
0.1
0.3
0.32
0.31
0.39
0.33
0.087
0.17
0.02
0.13
050G04
MO-001
SC-501-14
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w
M
b
1
e
D
A
2
Z
14
1
8
7
b
E
pin 1 index
0
5
10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
74HC_HCT08
All informatio
n provided in thi
s document is su
bject to legal
disclaimers.
© NXP B.V
. 201
2. All rights rese
rved.
Product data sheet
Rev
. 4 —
6 September 2012
9 of 16
NXP Semiconductors
74HC08; 74HCT08
Quad 2-input AND gate
Fig 9.
Package outline
SOT108-1 (SO14)
UNIT
A
max.
A
1
A
2
A
3
b
p
cD
(1)
E
(1)
(1)
eH
E
LL
p
QZ
y
w
v
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3
8
0
o
o
0.25
0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
w
M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
7
8
1
14
y
076E06
MS-012
pin 1 index
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.35
0.34
0.16
0.15
0.05
1.05
0.041
0.244
0.228
0.028
0.024
0.028
0.012
0.01
0.25
0.01
0.004
0.039
0.016
99-12-27
03-02-19
0
2.5
5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P16
74HC08N,652
Mfr. #:
Buy 74HC08N,652
Manufacturer:
NXP Semiconductors
Description:
Logic Gates QUAD 2-IN AND GATE
Lifecycle:
New from this manufacturer.
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