LPS331APY Datasheet LPS331APY, LPS331APTR | P10-P12

Digital interfaces LPS331AP

10/36 Doc ID 022112 Rev 7

5 Digital interfaces

5.1 I

C serial interface

The registers embedded in the LPS331AP may be accessed through both the I

C and SPI

serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire

interface mode.

The serial interfaces are mapped onto the same pads. To select/exploit the I

C interface, CS

line must be tied high (i.e. connected to Vdd_IO).

5.2 I

C serial interface

The LPS331AP I

C is a bus slave. The I

C is employed to write data into registers whose

content can also be read back.

The relevant I

C terminology is given in Table 8.

There are two signals associated with the I

C bus: the serial clock line (SCL) and the serial

data line (SDA). The latter is a bi-directional line used for sending and receiving the data

to/from the interface. Both lines have to be connected to Vdd_IO through pull-up resistors.

The I

C interface is compliant with fast mode (400 kHz) I

C standards as well as with the

normal mode.

Table 7. Serial interface pin description

Pin name Pin description

SPI enable

C/SPI mode selection (1: I

C mode; 0: SPI enabled)

SCL/

SPC

C serial clock (SCL)

SPI serial port clock (SPC)

SDA/

SDI/

SDO

C serial data (SDA)

SPI serial data input (SDI)

3-wire interface serial data output (SDO)

SA0/

SDO

C less significant bit of the device address (SA0)

SPI serial data output (SDO)

Table 8. Serial interface pin description

Term Description

Transmitter The device which sends data to the bus

Receiver The device which receives data from the bus

Master

The device which initiates a transfer, generates clock signals and terminates a

transfer

Slave The device addressed by the master

LPS331AP Digital interfaces

Doc ID 022112 Rev 7 11/36

5.2.1 I

C operation

The transaction on the bus is started through a START (ST) signal. A start condition is

defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After

this has been transmitted by the master, the bus is considered busy. The next byte of data

transmitted after the start condition contains the address of the slave in the first 7 bits and

the eighth bit tells whether the master is receiving data from the slave or transmitting data to

the slave. When an address is sent, each device in the system compares the first seven bits

after a start condition with its address. If they match, the device considers itself addressed

by the master.

The slave address (SAD) associated to the LPS331AP is 101110xb. The SDO/SA0 pad can

be used to modify the less significant bit of the device address. If the SA0 pad is connected

to voltage supply, LSb is ‘1’ (address 1011101b), otherwise if the SA0 pad is connected to

ground, the LSb value is ‘0’ (address 1011100b). This solution permits to connect and

address two different LPS331APs to the same I

C lines.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which

has been addressed is obliged to generate an acknowledge after each byte of data

received.

The I

C embedded in the LPS331AP behaves like a slave device and the following protocol

must be adhered to. After the start condition (ST) a slave address is sent, once a slave

acknowledge (SAK) has been returned, a 8-bit sub-address (SUB) will be transmitted: the 7

LSB represents the actual register address while the MSB enables address auto increment.

If the MSb of the SUB field is ‘1’, the SUB (register address) will be automatically increased

to allow multiple data read/write.

The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)

the master will transmit to the slave with direction unchanged. Ta bl e 9 explains how the

SAD+read/write bit pattern is composed, listing all the possible configurations.

Table 9. SAD+Read/Write patterns

Command SAD[6:1] SAD[0] = SA0 R/W SAD+R/W

Read 101110 0 1 10111001 (B9h)

Write 101110 0 0 10111000 (B8h)

Read 101110 1 1 10111011 (BBh)

Write 101110 1 0 10111010 (BAh)

Table 10. Transfer when master is writing one byte to slave

Master ST SAD + W SUB DATA SP

Slave SAK SAK SAK

Table 11. Transfer when master is writing multiple bytes to slave

Master ST SAD + W SUB DATA DATA SP

Slave SAK SAK SAK SAK

Digital interfaces LPS331AP

12/36 Doc ID 022112 Rev 7

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number

of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit

(MSb) first. If a receiver can’t receive another complete byte of data until it has performed

some other functions, it can hold the clock line, SCL LOW to force the transmitter into a wait

state. Data transfer only continues when the receiver is ready for another byte and releases

the data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to

receive because it is performing some real time function) the data line must be kept HIGH by

the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line

while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be

terminated by the generation of a STOP (SP) condition.

In order to read multiple bytes incrementing the register address, it is necessary to assert

the most significant bit of the sub-address field. In other words, SUB(7) must be equal to 1

while SUB(6-0) represents the address of the first register to be read.

In the presented communication format MAK is Master acknowledge and NMAK is no

master acknowledge.

5.3 SPI bus interface

The LPS331AP SPI is a bus slave. The SPI allows to write and read the registers of the

device.

The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.

Figure 4. Read and write protocol

CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of

the transmission and returns to high at the end. SPC is the serial port clock and it is

controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and

Table 12. Transfer when master is receiving (reading) one byte of data from slave

Master ST SAD + W SUB SR SAD + R NMAK SP

Slave SAK SAK SAK DATA

Table 13. Transfer when master is receiving (reading) multiple bytes of data from

slave

Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP

Slave SAK SAK SAK DATA DATA DATA

SPC

SDI

SDO

AD5 AD4 AD3 AD2 AD1 AD0

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