Semiconductor Components Industries, LLC, 2013
July, 2013 Rev. 11
1 Publication Order Number:
CAT5401/D
CAT5401
Quad Digital
Potentiometer (POT)
with 64 Taps
and SPI Interface
Description
The CAT5401 is four digital POTs integrated with control logic and
16 bytes of NVRAM memory. Each digital POT consists of a series of
63 resistive elements connected between two externally accessible end
points. The tap points between each resistive element are connected to
the wiper outputs with CMOS switches. A separate 6-bit control
register (WCR) independently controls the wiper tap switches for each
digital POT. Associated with each wiper control register are four 6-bit
non-volatile memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or any of the
non-volatile data registers is via a SPI serial bus. On power-up, the
contents of the first data register (DR0) for each of the four
potentiometers is automatically loaded into its respective wiper
control register.
The CAT5401 can be used as a potentiometer or as a two terminal,
variable resistor. It is intended for circuit level or system level
adjustments in a wide variety of applications.
Features
Four Linear Taper Digital Potentiometers
64 Resistor Taps per Potentiometer
End to End Resistance 2.5 kW, 10 kW, 50 kW or 100 kW
Potentiometer Control and Memory Access via SPI Interface:
Mode (0, 0) and (1, 1)
Low Wiper Resistance, Typically 100 W
Nonvolatile Memory Storage for up to Four Wiper Settings for Each
Potentiometer
Automatic Recall of Saved Wiper Settings at Power Up
2.5 to 6.0 Volt Operation
Standby Current Less than 1 mA
1,000,000 Nonvolatile WRITE Cycles
100 Year Nonvolatile Memory Data Retention
24-lead SOIC and 24-lead TSSOP
Industrial Temperature Range
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
TSSOP24
Y SUFFIX
CASE 948AR
PIN CONNECTIONS
SOIC24 (W)
(Top View)
NC
V
CC
R
L0
R
H0
1
R
W0
CS
R
L3
R
H3
R
W3
A
0
SOIC24
W SUFFIX
CASE 751BK
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
ORDERING INFORMATION
SO
HOLD
SCK
R
L2
R
H2
WP
SI
A
1
R
L1
R
H1
CAT5401
R
W2
NC
R
W1
GND
TSSOP24 (Y)
(Top View)
CAT5401
WP
CS
R
W0
R
H0
R
L0
V
CC
NC
R
L3
R
H3
R
W3
A
0
SO
SI
A
1
R
L1
R
H1
R
W1
GND
NC
R
W2
R
H2
R
L2
SCK
HOLD
1
CAT5401
http://onsemi.com
2
L = Assembly Location
3 = Lead Finish Matte-Tin
B = Product Revision (Fixed as “B”)
CAT = Fixed as “CAT”
5401W = Device Code
T = Temperature Range (I = Industrial)
= Dash
RR = Resistance
25 = 2.5 KW
10 = 10 KW
50 = 50 KW
00 = 100 KW
Y = Production Year (Last Digit)
M = Production Month (19, O, N, D)
XXXX = Last Four Digits of Assembly Lot Number
L3B
CAT5401WT
RRYMXXXX
R = Resistance
1 = 2.5 KW
2 = 10 KW
4 = 50 KW
5 = 100 KW
L = Assembly Location
B = Product Revision (Fixed as “B”)
CAT5401Y = Device Code
T = Temperature Range (I = Industrial)
3 = Lead Finish Matte-Tin
Y = Production Year (Last Digit)
M = Production Month (19, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
RLB
CAT5401YT
3YMXXX
MARKING DIAGRAMS
(TSSOP24)(SOIC24)
Figure 1. Functional Diagram
NONVOLATILE
DATA
REGISTERS
CONTROL
LOGIC
WIPER
REGISTERS
SPI BUS
INTERFACE
SCK
SI
SO
R
W0
R
W1
R
W2
R
W3
R
L3
R
L2
R
L1
R
L0
R
H3
R
H2
R
H1
R
H0
CS
WP
A
0
A
1
CONTROL
CAT5401
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3
PIN DESCRIPTIONS
Table 1. PIN DESCRIPTIONS
Pin#
(SOIC)
Pin#
(TSSOP)
Name Function
1 19 V
CC
Supply Voltage
2 20 R
L0
Low Reference Terminal
for Potentiometer 0
3 21 R
H0
High Reference Terminal
for Potentiometer 0
4 22 R
W0
Wiper Terminal for
Potentiometer 0
5 23 CS Chip Select
6 24 WP Write Protection
7 1 SI Serial Input
8 2 A1 Device Address
9 3 R
L1
Low Reference Terminal
for Potentiometer 1
10 4 R
H1
High Reference Terminal
for Potentiometer 1
11 5 R
W1
Wiper Terminal for
Potentiometer 1
12 6 GND Ground
13 7 NC No Connect
14 8 R
W2
Wiper Terminal for
Potentiometer 2
15 9 R
H2
High Reference Terminal
for Potentiometer 2
16 10 R
L2
Low Reference Terminal
for Potentiometer 2
17 11 SCK Bus Serial Clock
18 12 HOLD Hold
19 13 SO Serial Data Output
20 14 A0 Device Address, LSB
21 15 R
W3
Wiper Terminal for
Potentiometer 3
22 16 R
H3
High Reference Terminal
for Potentiometer 3
23 17 R
L3
Low Reference Terminal
for Potentiometer 3
24 18 NC No Connect
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses and data to be written to the
CAT5401. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the CAT5401. During a read cycle, data is shifted
out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT5401. Opcodes, byte addresses or data present on the SI
pin are latched on the rising edge of the SCK. Data on the SO
pin is updated on the falling edge of the SCK.
A0, A1: Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of four devices can be addressed on
a single bus. A match in the slave address must be made with
the address input in order to initiate communication with the
CAT5401.
R
H
, R
L
: Resistor End Points
The four sets of R
H
and R
L
pins are equivalent to the
terminal connections on a mechanical potentiometer.
R
W
: Wiper
The four R
W
pins are equivalent to the wiper terminal of
a mechanical potentiometer.
CS
: Chip Select
CS
is the Chip select pin. CS low enables the CAT5401
and CS
high disables the CAT5401. CS high takes the SO
output pin to high impedance and forces the devices into a
Standby mode (unless an internal write operation is
underway). The CAT5401 draws ZERO current in the
Standby mode. A high to low transition on CS
is required
prior to any sequence being initiated. A low to high
transition on CS
after a valid write sequence is what initiates
an internal write cycle.
WP
: Write Protect
WP
is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high. When
WP
is tied low, all non-volatile write operations to the Data
registers are inhibited (change of wiper control register is
allowed). WP
going low while CS is still low will interrupt
a write to the registers. If the internal write cycle has already
been initiated, WP
going low will have no effect on any write
operation.
HOLD
: Hold
The HOLD
pin is used to pause transmission to the
CAT5401 while in the middle of a serial sequence without
having to retransmit entire sequence at a later time. To pause,
HOLD
must be brought low while SCK is low. The SO pin
is in a high impedance state during the time the part is
paused, and transitions on the SI pins will be ignored. To
resume communication, HOLD
is brought high, while SCK
is low. (HOLD
should be held high any time this function is
not being used.) HOLD
may be tied high directly to V
CC
or
tied to V
CC
through a resistor.

CAT5401YI-25-T2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Digital Potentiometer ICs DPP,NV,Quad 64 taps SPI
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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