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CAT5401YI-25-T2

P1-P3P4-P6P7-P9P10-P12P13-P15
CAT5401
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7
Figure 2. Synchronous Data Timing
VALID IN
HI−Z
HI−Z
SCK
SI
SO
Figure 3. HOLD Timing
SCK
SO
HIGH IMPEDANCE
t
DIS
t
HO
t
CSH
t
CS
t
WL
t
V
t
RI
t
FI
t
WH
t
H
t
SU
V
IH
V
IL
CS
t
CSS
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
t
CD
t
HD
t
LZ
t
HZ
t
HD
t
CD
HOLD
CS
10.This parameter is tested initially and after a design or process change that affects the parameter.
11. Dashed Line = mode (1, 1) − − − − − − −
CAT5401
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8
INSTRUCTION AND REGISTER DESCRIPTION
Device Type/Address Byte
The first byte sent to the CAT5401 from the master/
processor is called the Device Address Byte. The most
significant four bits of the Device Type address are a device
type identifier. These bits for the CAT5401 are fixed at
0101[B] (refer to Figure 4).
The two least significant bits in the slave address byte, A1
− A0, are the internal slave address and must match the
physical device address which is defined by the state of the
A1 − A0 input pins for the CAT5401 to successfully continue
the command sequence. Only the device which slave
address matches the incoming device address sent by the
master executes the instruction. The A1 − A0 inputs can be
actively driven by CMOS input signals or tied to V
CC
or
V
SS
. The remaining two bits in the device address byte must
be set to 0.
Instruction Byte
The next byte sent to the CAT5401 contains the
instruction and register pointer information. The four most
significant bits used provide the instruction opcode I [3:0].
The R1 and R0 bits point to one of the four data registers of
each associated potentiometer. The least two significant bits
point to one of four Wiper Control Registers. The format is
shown in Figure 5.
Table 11. DATA REGISTER SELECTION
Data Register Selected R1 R0
DR0 0 0
DR1 0 1
DR2 1 0
DR3 1 1
Figure 4. Identification Byte Format
ID3 ID2 ID1 ID0 0 0 A1 A0
0101
(MSB) (LSB)
DeviceType
Identifier
SlaveAddress
Figure 5. Instruction Byte Format
I3 I2 I1 I0 R1 R0 P1 P0
(MSB) (LSB)
WCR/Pot Selection
Instruction
Opcode
Data Register
Selection
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
The CAT5401 contains four 6-bit Wiper Control
Registers, one for each potentiometer. The Wiper Control
Register output is decoded to select one of 64 switches along
its resistor array. The contents of the WCR can be altered in
four ways: it may be written by the host via Write Wiper
Control Register instruction; it may be written by
transferring the contents of one of four associated Data
Registers via the XFR Data Register instruction, it can be
modified one step at a time by the Increment/decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the content of its data register zero
(DR0) upon power-up.
The Wiper Control Register is a volatile register that loses
its contents when the CAT5401 is powered-down. Although
the register is automatically loaded with the value in DR0
upon power-up, this may be different from the value present
at power-down.
Data Registers (DR)
Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the associated Wiper Control Register. Any
data changes in one of the Data Registers is a non−volatile
operation and will take a maximum of 5 ms.
Write In Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS
input goes HIGH after a
write sequence is received. The status of the internal write
cycle can be monitored by issuing a Read Status command
to read the Write in Process (WIP) bit.
Instructions
Four of the nine instructions are three bytes in length.
These instructions are:
CAT5401
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Read Wiper Control Register – read the current wiper
position of the selected potentiometer in the WCR
Write Wiper Control Register – change current wiper
position in the WCR of the selected potentiometer
Read Data Register – read the contents of the selected
Data Register
Write Data Register – write a new value to the
selected Data Register
Read Status – Read the status of the WIP bit which
when set to “1” signifies a write cycle is in progress.
Table 12. INSTRUCTION SET (Note: 1/0 = data is one or zero)
Instruction
Instruction Set
Operation
I3 I2 I1 I0 R1 R0 WCR1/ P1 WCR0/ P0
Read Wiper Control
Register
1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper Control
Register pointed to by P1−P0
Write Wiper Control
Register
1 0 1 0 0 0 1/0 1/0 Write new value to the Wiper Control
Register pointed to by P1−P0
Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register
pointed to by P1−P0 and R1−R0
Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register
pointed to by P1−P0 and R1−R0
XFR Data Register to
Wiper Control Register
1 1 0 1 1/0 1/0 1/0 1/0 Transfer the contents of the Data
Register pointed to by P1−P0 and
R1−R0 to its associated Wiper Control
Register
XFR Wiper Control
Register to Data
Register
1 1 1 0 1/0 1/0 1/0 1/0 Transfer the contents of the Wiper
Control Register pointed to by P1−P0 to
the Data Register pointed to by R1−R0
Global XFR Data
Registers to Wiper
Control Registers
0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data
Registers pointed to by R1−R0 of all four
pots to their respective Wiper Control
Registers
Global XFR Wiper
Control Registers to
Data Register
1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper
Control Registers to their respective data
Registers pointed to by R1−R0 of all four
pots
Increment/Decrement
Wiper Control Register
0 0 1 0 0 0 1/0 1/0 Enable Increment/decrement of the
Control Latch pointed to by P1−P0
Read Status (WIP bit) 0 1 0 1 0 0 0 1 Read WIP bit to check internal write
cycle status
The basic sequence of the three byte instructions is
illustrated in Figure 7. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper. The
response of the wiper to this action will be delayed by t
WRL
.
A transfer from the WCR (current wiper position), to a Data
Register is a write to non-volatile memory and takes a
minimum of t
WR
to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or the transfer can occur between all
potentiometers and one associated register.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 6. These instructions
transfer data between the host/processor and the CAT5401;
either between the host and one of the data registers or
directly between the host and the Wiper Control Register.
These instructions are:
XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
Gang XFR Data Register to Wiper Control Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control Registers.
Gang XFR Wiper Counter Register to Data Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data Registers.
P1-P3P4-P6P7-P9P10-P12P13-P15

CAT5401YI-25-T2

Mfr. #:
Buy CAT5401YI-25-T2
Manufacturer:
ON Semiconductor
Description:
Digital Potentiometer ICs DPP,NV,Quad 64 taps SPI
Lifecycle:
New from this manufacturer.
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