CAT5401
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10
Increment/Decrement Command
The final command is Increment/Decrement (Figure 8).
The Increment/Decrement command is different from the
other commands. Once the command is issued the master
can clock the selected wiper up and/or down in one segment
steps; thereby providing a fine tuning capability to the host.
For each SCK clock pulse (t
HIGH
) while SI is HIGH, the
selected wiper will move one resistor segment towards the
R
H
terminal. Similarly, for each SCK clock pulse while SI
is LOW, the selected wiper will move one resistor segment
towards the R
L
terminal.
See Instructions format for more detail.
Figure 6. Two-byte Instruction Sequence
0101
A2 A0
I2 I1 I0
R1 R0 P1
SI
ID3 ID2 ID1 ID0
P0
Device ID
Internal
Instruction
Opcode
Address
Register
Address
Pot/WCR
Address
A1A3
I3
00
Figure 7. Three-byte Instruction Sequence
I3 I2 I1 I0
R1 R0
ID3 ID2 ID1 ID0
Device ID
Internal
Instruction
Opcode
Address
Data
Register
Address
Pot/WCR
Address
WCR[7:0]
or
Data Register D[7:0]
0 10100
A2 A1 A0
P1 P0
SI
D7 D6 D5 D4 D3 D2 D1 D0
A3
Figure 8. Increment/Decrement Instruction Sequence
I3 I2 I1 I0
ID3 ID2 ID1 ID0
Device ID
Internal
Instruction
Opcode
Address
Data
Register
Address
Pot/WCR
Address
010 100
A2 A1 A0
R0 P1 P0
SI
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
R1
A3
Figure 9. Increment/Decrement Timing Limits
SCK
SI
INC/DEC
Command
Issued
Voltage Out
t
WRID
R
W
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11
INSTRUCTION FORMAT
Table 13. READ WIPER CONTROL REGISTER (WCR)
CS
DEVICE ADDRESSES INSTRUCTION DATA
CS
0 1 0 1 0 0 A1 A0 1 0 0 1 0 0 P1 P0 7 6 5 4 3 2 1 0
0 0
Table 14. WRITE WIPER CONTROL REGISTER (WCR)
CS
DEVICE ADDRESSES INSTRUCTION DATA
CS
0 1 0 1 0 0 A1 A0 1 0 1 0 0 0 P1 P0 7 6 5 4 3 2 1 0
0 0
Table 15. READ DATA REGISTER (DR)
CS
DEVICE ADDRESSES INSTRUCTION DATA
CS
0 1 0 1 0 0 A1 A0 1 0 1 1 R1 R0 P1 P0 7 6 5 4 3 2 1 0
Table 16. WRITE DATA REGISTER (DR)
CS
DEVICE ADDRESSES INSTRUCTION DATA
CS
High
Voltage
Write
Cycle
0 1 0 1 0 0 A1 A0 1 1 0 0 R1 R0 P1 P0 7 6 5 4 3 2 1 0
Table 17. READ STATUS (WIP)
CS
DEVICE ADDRESSES INSTRUCTION DATA
CS
0 1 0 1 0 0 A1 A0 0 1 0 1 0 0 0 1 7 6 5 4 3 2 1 W
0 0 0 0 0 0 0 I
P
Table 18. GLOBAL TRANSFER DATA REGISTER (DR) TO WIPER CONTROL REGISTER (WCR)
CS
DEVICE ADDRESSES INSTRUCTION
CS
0 1 0 1 0 0 A1 A0 0 0 0 1 R1 R0 0 0
Table 19. GLOBAL TRANSFER WIPER CONTROL REGISTER (WCR) TO DATA REGISTER (DR)
CS
DEVICE ADDRESSES INSTRUCTION
CS
High
Voltage
Write
Cycle
0 1 0 1 0 0 A1 A0 1 0 0 0 R1 R0 0 0
CAT5401
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Table 20. TRANSFER WIPER CONTROL REGISTER (WCR) TO DATA REGISTER (DR)
CS
DEVICE ADDRESSES INSTRUCTION
CS
High
Voltage
Write
Cycle
0 1 0 1 0 0 A1 A0 1 1 1 0 R1 R0 P1 P0
Table 21. TRANSFER DATA REGISTER (DR) TO WIPER CONTROL REGISTER (WCR)
CS
DEVICE ADDRESSES INSTRUCTION
CS
0 1 0 1 0 0 A1 A0 1 1 0 1 R1 R0 P1 P0
Table 22. INCREMENT (I)/DECREMENT (D) WIPER CONTROL REGISTER (WCR)
CS
DEVICE ADDRESSES INSTRUCTION DATA
CS
0 1 0 1 0 0 A1 A0 0 0 1 0 0 0 P1 P0 I/D I/D . . . I/D I/D
NOTE: Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after CS goes high.

CAT5401YI-50-T2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Digital Potentiometer ICs DPP,NV,Quad 64 taps SPI
Lifecycle:
New from this manufacturer.
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