CAT5401
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SERIAL BUS PROTOCOL
The CAT5041 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface (SPI)
helps the CAT5401 to interface directly with many of
today’s popular microcontrollers. The CAT5041 contains an
8bit instruction register. The instruction set and the
operation codes are detailed in the instruction set Table 12.
After the device is selected with CS
going low the first
byte will be received. The part is accessed via the SI pin, with
data being clocked in on the rising edge of SCK. The first
byte contains one of the six op-codes that define the
operation to be performed.
DEVICE OPERATION
The CAT5401 is four resistor arrays integrated with SPI
serial interface logic, four 6-bit wiper control registers and
sixteen 6-bit, non-volatile memory data registers. Each
resistor array contains 63 separate resistive elements
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
). R
H
and R
L
are symmetrical and
may be interchanged. The tap positions between and at the
ends of the series resistors are connected to the output wiper
terminals (R
W
) by a CMOS transistor switch. Only one tap
point for each potentiometer is connected to its wiper
terminal at a time and is determined by the value of the wiper
control register. Data can be read or written to the wiper
control registers or the non-volatile memory data registers
via the SPI bus. Additional instructions allows data to be
transferred between the wiper control registers and each
respective potentiometers non-volatile data registers. Also,
the device can be instructed to operate in an “increment/
decrement” mode.
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Temperature Under Bias 55 to +125 C
Storage Temperature 65 to +150 C
Voltage on Any Pin with Respect to V
SS
(Notes 1, 2) 2.0 to +V
CC
+ 2.0 V
V
CC
with Respect to Ground 0.2 to +7.0 V
Package Power Dissipation Capability (T
A
= 25C) 1.0 W
Lead Soldering Temperature (10 s) 300 C
Wiper Current 12 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5 V, which may overshoot to V
CC
+2.0 V for periods of less than 20 ns.
2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V
CC
+1 V.
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameters Ratings Units
V
CC
+2.5 to +6 V
Industrial Temperature 40 to +85 C
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Table 4. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter Test Conditions Min Typ Max Units
R
POT
Potentiometer Resistance (00) 100
kW
R
POT
Potentiometer Resistance (50) 50
kW
R
POT
Potentiometer Resistance (10) 10
kW
R
POT
Potentiometer Resistance (2.5) 2.5
kW
Potentiometer Resistance Tolerance 20 %
R
POT
Matching 1 %
Power Rating 25C, each pot 50 mW
I
W
Wiper Current +3 mA
R
W
Wiper Resistance I
W
= 3 mA @ V
CC
= 3 V 200 300
W
R
W
Wiper Resistance I
W
= 3 mA @ V
CC
= 5 V 100 150
W
V
TERM
Voltage on any R
H
or R
L
Pin V
SS
= 0 V GND V
CC
V
VN Noise (Note 3) nVHz
Resolution 0.4 %
Absolute Linearity (Note 4) R
W
(n)(actual) R(n)(expected)
(Note 7)
+1 LSB
(Note 6)
Relative Linearity (Note 5) R
W
(n+1) [R
W
(n) + LSB]
(Note 7)
+0.2 LSB
(Note 6)
TC
RPOT
Temperature Coefficient of R
POT
(Note 3) +300 ppm/C
TC
RATIO
Ratiometric Temp. Coefficient (Note 3) 20 ppm/C
C
H
/C
L
/C
W
Potentiometer Capacitances (Note 3) 10/10/25 pF
fc Frequency Response
R
POT
= 50 kW (Note 3)
0.4 MHz
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
It is a measure of the error in step size.
6. LSB = R
TOT
/ 63 or (R
H
R
L
) / 63, single pot
7. n = 0, 1, 2, ..., 63
Table 5. D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter Test Conditions Min Max Units
I
CC
Power Supply Current f
SCL
= 2 MHz, SO = Open
Inputs = GND
1 mA
I
SB
Standby Current (V
CC
= 5 V) V
IN
= GND or V
CC
, SO = Open 1
mA
I
LI
Input Leakage Current V
IN
= GND to V
CC
10
mA
I
LO
Output Leakage Current V
OUT
= GND to V
CC
10
mA
V
IL
Input Low Voltage 1 V
CC
x 0.3 V
V
IH
Input High Voltage V
CC
x 0.7 V
CC
+ 1.0 V
V
OL1
Output Low Voltage (V
CC
= 3 V) I
OL
= 3 mA 0.4 V
Table 6. PIN CAPACITANCE (Note 8)
(Available over recommended operating range from T
A
= 25C, f = 1.0 MHz, V
CC
= 5 V (unless otherwise noted).)
Symbol
Test Conditions Max Units
C
OUT
Output Capacitance (SO) V
OUT
= 0 V 8 pF
C
IN
Input Capacitance (CS, SCK, SI, WP, HOLD) V
IN
= 0 V 6 pF
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Table 7. A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter Test Conditions Min Typ Max Units
t
SU
Data Setup Time
C
L
= 50 pF
50 ns
t
H
Data Hold Time 50 ns
t
WH
SCK High Time 125 ns
t
WL
SCK Low Time 125 ns
f
SCK
Clock Frequency DC 3 MHz
t
LZ
HOLD to Output Low Z 50 ns
t
RI
(Note 8) Input Rise Time 2
ms
t
FI
(Note 8) Input Fall Time 2
ms
t
HD
HOLD Setup Time 100 ns
t
CD
HOLD Hold Time 100 ns
t
V
Output Valid from Clock Low 250 ns
t
HO
Output Hold Time 0 ns
t
DIS
Output Disable Time 250 ns
t
HZ
HOLD to Output High Z 100 ns
t
CS
CS High Time 250 ns
t
CSS
CS Setup Time 250 ns
t
CSH
CS Hold Time 250 ns
Table 8. POWER UP TIMING (Notes 8, 9)
Symbol
Parameter Max Units
t
PUR
Power-up to Read Operation 1 ms
t
PUW
Power-up to Write Operation 1 ms
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. t
PUR
and t
PUW
are delays required from the time V
CC
is stable until the specified operation can be initiated.
Table 9. WRITE CYCLE LIMITS
Symbol Parameter Max Units
t
WR
Write Cycle Time 5 ms
Table 10. RELIABILITY CHARACTERISTICS
Symbol Parameter Reference Test Method Min Max Units
N
END
(Note 10) Endurance MILSTD883, Test Method 1033 1,000,000 Cycles/Byte
T
DR
(Note 10) Data Retention MILSTD883, Test Method 1008 100 Years
V
ZAP
(Note 10) ESD Susceptibility MILSTD883, Test Method 3015 2000 V
I
LTH
(Note 10) Latch-up JEDEC Standard 17 100 mA

CAT5401YI-50-T2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Digital Potentiometer ICs DPP,NV,Quad 64 taps SPI
Lifecycle:
New from this manufacturer.
Delivery:
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