LTC3852
10
3852f
PIN FUNCTIONS
C
(Pin 8): Flying Capacitor Negative Terminal.
SHDN (Pin 10): Active Low Shutdown Input. A low on
SHDN disables the charge pump. This pin must not be
allowed to fl oat.
GND1 (Pin 11): Charge Pump Ground. The (–) terminals of
C
IN
and C
VPUMP
should be closely connected to this pin.
V
IN1
(Pin 12): Input Supply Voltage to Charge Pump. V
IN1
should be bypassed with a 1F to 4.7F low ESR ceramic
capacitor.
V
PUMP
(Pin 13): Regulated Output Voltage from Charge
Pump. For best performance, V
PUMP
should be bypassed
with a low ESR ceramic capacitor providing at least 2.2F
of capacitance as close to the pin as possible.
INTV
CC
(Pin 14): Gate Drive Supply. The MOSFET drivers
and internal logic are powered from this voltage. Bypass
this pin to GND with a minimum 2.2F low ESR tantalum
or ceramic capacitor, C
INTVCC
.
V
IN2
(Pin 15): Main Supply Pin for Step-Down Controller.
A bypass capacitor should be tied between this pin and
the GND2 pin.
BOOST (Pin 16): Boosted Floating Driver Supply. The
(+) terminal of the booststrap capacitor is connected to
this pin. This pin swings from a diode voltage drop below
INTV
CC
up to V
IN1
+ INTV
CC
.
TG (Pin 17): Top Gate Driver Output. This is the output
of a fl oating driver with a voltage swing equal to INTV
CC
superimposed on the switch node voltage.
SW (Pin 18): Switch Node Connection to the Inductor. Vol-
tage swing at this pin is from a diode (external) voltage drop
below ground to the buck regulator power stage V
IN
.
MODE/PLLIN (Pin 19): Forced Continuous Mode, Burst
Mode operation or Pulse-Skipping Mode Selection Pin
and External Synchronization Input to Phase Detector
Pin. Connect this pin to INTV
CC
to force continuous
conduction mode of operation. Connect to GND2 to enable
pulse-skipping mode of operation. To select Burst Mode
operation, tie this pin to INTV
CC
through a resistor no less
than 50k, but no greater than 250k. A clock on the pin
will force the controller into forced continuous mode of
operation and synchronize the internal oscillator.
FREQ/PLLFLTR (Pin 20): The phase-locked loop’s lowpass
lter is tied to this pin. Alternatively, a resistor can be
connected between this pin and GND2 to vary the frequency
of the internal oscillator.
RUN (Pin 21): Run Control Input. Forcing the pin below
1.25V shuts down the step-down controller. There is a
2µA pull-up current on this pin.
TRACK/SS (Pin 22): Output Voltage Tracking and Soft-Start
Input. A capacitor to ground at this pin sets the ramp rate
for the output voltage. An internal soft-start current of 1A
charges this capacitor.
I
TH
(Pin 23): Error Amplifi er Output and Switching
Regulator Compensation Point. The current comparator
input threshold increases with this control voltage.
V
FB
(Pin 24): Error Amplifi er Feedback Input. This pin
receives the remotely sensed feedback voltage from an
external resistive divider across the output.
GND (Exposed Pad Pin 25): Ground. Must be soldered to
PCB, providing a local ground for the IC.
LTC3852
11
3852f
FUNCTIONAL DIAGRAM
+
+
+
2µA
SLOPE COMPENSATION
UVLO
OSC
S
RQ
5k
RUN
SWITCH
LOGIC
AND
ANTI-
SHOOT
THROUGH
BG
ON
PULSE SKIP
0.8V
OV
1
100k
1.25V0.64V
R
C
INTV
CC
I
THB
I
CMP
C
C1
EA
SS
R1
0.88V
R2
GND2
SW
TG
C
B
V
IN2
SLEEP
BOOST
BURSTEN
+
+
UV
OV
C
INTVCC
V
OUT
C
OUT
M2
M1
L1
+
I
REV
D
B
MODE/PLLIN
BUCK REGULATOR
100k
SENSE
+
SENSE
0.8V
REF
TRACK/SS
0.4V
+
V
FB
FREQ/
PLLFLTR
PLL-SYNC
5V REG
MODE/SYNC
DETECT
+
1µA
C
SS
+
PGOOD
+
0.72V
V
IN
38V MAX
+
V
PUMP
RUN
C
PUMP
V
IN1
V
IN1
2.7V to 5.5V
C
IN
SHDN
C
+
C
CHARGE
PUMP
1.2MHz
OSCILLATO
CHARGE PUMP
R
GND1
ON/OFF
C
FLY
3852 FD
INTV
CC
I
TH
V
IN2
FAULT
LOGIC
RUN
+
SOFT-START
AND
SWITCH CONTROL
LTC3852
12
3852f
OPERATION
Main Control Loop
The LTC3852 is a constant frequency, current mode
step-down DC/DC controller which can be powered by
an onboard charge pump. Supplies as low as 2.7V, when
doubled by the charge pump, provide 5V to the LTC3852’s
control logic and gate drives, supporting a wide selection
of logic-level MOSFETs.
During normal operation, the controllers top MOSFET is
turned on when the clock sets the RS latch, and is turned
off when the main current comparator, I
CMP
, resets the
RS latch. The peak inductor current at which I
CMP
resets
the RS latch is controlled by the voltage on the I
TH
pin,
which is the output of the error ampli er EA. The V
FB
pin
receives the voltage feedback signal, which is compared
to the internal reference voltage by the EA. When the
load current increases, it causes a slight decrease in V
FB
relative to the 0.8V reference, which in turn causes the
I
TH
voltage to increase until the average inductor current
matches the new load current. After the top MOSFET has
turned off, the bottom MOSFET is turned on until either
the inductor current starts to reverse, as indicated by the
reverse current comparator, I
REV
, or the beginning of the
next cycle.
The charge pump section uses a switched capacitor doubler
to boost V
IN1
to 2 ¥ V
IN1
, with a regulated maximum of
5V. Regulation is achieved by sensing the output voltage
through an internal resistor divider and modulating the
charge pump output current based on the error signal. A
2-phase nonoverlapping clock activates the charge pump
switches. The fl ying capacitor is charged from V
IN1
on
the fi rst phase of the clock. On the second phase of the
clock it is stacked in series with V
IN1
and connected to
V
PUMP
. This sequence of charging and discharging the
ying capacitor continues at a free running frequency of
1.2MHz (typ).
Two confi gurations address most LTC3852 applications.
Figure 1a covers the single low input voltage case, typically
3.3V. The input to the charge pump, V
IN1
, is connected to
the same input voltage as the drain of the top MOSFET.
V
PUMP
, V
IN2
and INTV
CC
are tied together, so that the
charge pump’s 5V output provides all power to the buck
controller section.
The alternative arrangement in Figure 1b allows the
LTC3852 to step down from as high as 38V, while powering
itself from an available 3.3V bus. The input to the charge
pump, V
IN1
, is connected to 3.3V instead of the drain of
the top MOSFET. It is not necessary to step the high input
voltage down to 5V through a linear regulator. Logic level
MOSFETs are usable in both cases.
V
IN
3.3V
3852 F01a
V
IN1
V
PUMP
V
IN2
INTV
CC
TG
BG
Figure 1a
V
IN
≤ 38V
3852 F01b
V
IN1
V
PUMP
V
IN2
INTV
CC
TG
BG
3.3V
Figure 1b
INTV
CC
Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTV
CC
pin. Peak
current drawn from INTV
CC
should not exceed 50mA.
The top MOSFET driver is biased from the fl oating boot-
strap capacitor, C
B
, which normally recharges during each
off cycle through an external diode when the top MOSFET
turns off. If V
IN
decreases to a voltage close to V
OUT
, the
loop may enter dropout and attempt to turn on the top
MOSFET continuously. The dropout detec tor detects this
and forces the top MOSFET off for about 1/10 of the clock
period every tenth cycle to allow C
B
to recharge. However, it

LTC3852EUDD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Low Input Voltage Synchronous Step-Down Controller
Lifecycle:
New from this manufacturer.
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