LTC3852
28
3852f
will improve performance and ensure proper regulation
under all conditions. Figure 15 shows an example layout
for the charge pump.
APPLICATIONS INFORMATION
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between C
IN
, the Schottky and the
top MOSFET to the sensitive current and voltage sensing
traces. In addition, investigate common ground path
voltage pickup between these components and the GND
pin of the IC.
Design Example
As a design example, assume V
IN
= 3.3V (nominal), V
IN
=
5.5V (maximum), V
OUT
= 1.5V, I
MAX
= 15A, and f = 400kHz
(refer to Figure 16).
The inductance value is chosen fi rst based on a 30%
ripple current assumption. The highest value of ripple
current occurs at the maximum input voltage. Connect
a 68.1k resistor between the FREQ/PLLFLTR and GND
pins, generating 400kHz op eration. The inductance for
30% ripple current is:
L =
1
ΔI
L
f
()
V
OUT
1−
V
OUT
V
IN
⎛
⎝
⎜
⎞
⎠
⎟
=
1
4.5A 400kHz
()
1.5V 1−
1.5V
3.3V
⎛
⎝
⎜
⎞
⎠
⎟
= 454nH
A 400nH inductor will produce 34% ripple current.The peak
inductor current will be the maximum DC value (15A) plus
one-half the ripple current (2.5A), or 17.5A. The minimum
on-time occurs at maximum V
IN
:
t
ON(MIN)
=
V
OUT
V
IN(MAX)
f
()
=
1.5V
5.5V 400kHz
()
= 682ns
which is greater than the 90ns minimum on-time.
The R
SENSE
resistor value can be calculated by using the
minimum current sense voltage specifi cation with a 20%
increase for current limit.
R
SENSE
≤
V
SENSE(MIN)
I
PEAK
•1.2
≤
40mV
17.5A • 1.2
= 1.9mΩ
Choosing 1% resistors: R1 = 20k and R2 = 37.4k yields
an output voltage of 1.496V.
Figure 15. Recommended Charge Pump Layout
3852 F15
C
IN
0603
C
PUMP
0603
V
PUMP
V
IN1
C
FLY
0603
GND1
LTC3852EUDD
C
+
C
–
PC Board Layout Debugging
It is helpful to use a DC-50MHz current probe to monitor
the current in the inductor while testing the circuit. Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator and probe the actual
output voltage as well. Check for proper performance
over the operating voltage and current range expected
in the application. The frequency of operation should be
maintained over the input voltage range down to dropout
and until the output load drops below the low current
operation threshold—typically 10% of the maximum
designed cur rent level in Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well designed, low noise PCB imple mentation.
Variation in the duty cycle at a subharmonic rate can suggest
noise pick-up at the current or voltage sensing inputs or
inadequate loop compensation. Overcompensation of the
loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
