204Pin DDR3L 1600 SO-DIMM
2GB Based on 256Mx8
AQD-SD3L2GN16-SQ
Differential Input Logical High
Differential Input Logical Low
IDD Specification parameters Definition( IDD values are for full operating range of Voltage and Temperature)
2GB, 256Mx64 Module(1 Rank x8)
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC =
tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid
commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL =
8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD),
tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as IDD4W
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is
HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
/CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Active standby current; All banks open; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT
= 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD),
tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL =
8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING IDD4R
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD)
interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, IOUT =
0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc =
tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH
between valid commands;Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R;
1.Module IDD was calculated on the specific brand DRAM(4xnm) component IDD and can be differently
measured according to DQ loading capacitor.
Timing Parameters & Specifications
